TMS320C6747

Name: TMS320C6747
Brand: TI
SKU: TMS320C6747
Price: 10.322 USD

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DSP de punto flotante C674x de 456 MHz y baja potencia, con PBGA

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Hoja de datos

document-pdfAcrobat TMS320C6745, TMS320C6747 Fixed- and Floating-Point Digital Signal Processor datasheet (Rev. F) (Inglés) PDF | HTML

Guías de usuario

document-pdfAcrobat
TMS320C6745/C6747 DSP Technical Reference Manual (Rev. D) (Inglés)

Errata

document-pdfAcrobat
TMS320C6747 Fixed/Floating-Point DSP SE (Silicon Revs 3.0, 2.1, 2.0, 1.1, & 1.0) (Rev. G) (Inglés)

TMS320C6747

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Hoja de datos

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Detalles del producto

CPU

32-/64-bit

Frequency (MHz)

375, 456

Display type

Features

1 RTC, 3 enhanced-capture peripherals

Operating system

SYS/BIOS

Rating

Catalog

Operating temperature range (°C)

-40 to 125

CPU

32-/64-bit

Frequency (MHz)

375, 456

Display type

Features

1 RTC, 3 enhanced-capture peripherals

Operating system

SYS/BIOS

Rating

Catalog

Operating temperature range (°C)

-40 to 125

PBGA (ZKB)

256

289 mm² 17 x 17

Software Support
- TI DSP/BIOS™
- Chip Support Library and DSP Library
375- and 456-MHz TMS320C674x VLIW DSP
C674x Instruction Set Features
- Superset of the C67x+ and C64x+ ISAs
- Up to 3648 MIPS and 2736 MFLOPS C674x
- Byte-Addressable (8-, 16-, 32-, and 64-Bit Data)
- 8-Bit Overflow Protection
- Bit-Field Extract, Set, Clear
- Normalization, Saturation, Bit-Counting
- Compact 16-Bit Instructions
C674x Two-Level Cache Memory Architecture
- 32KB of L1P Program RAM/Cache
- 32KB of L1D Data RAM/Cache
- 256KB of L2 Unified Mapped RAM/Cache
- Flexible RAM/Cache Partition (L1 and L2)
Enhanced Direct Memory Access Controller 3 (EDMA3):
- 2 Transfer Controllers
- 32 Independent DMA Channels
- 8 Quick DMA Channels
- Programmable Transfer Burst Size
TMS320C674x Fixed- and Floating-Point VLIW DSP Core
- Load-Store Architecture with Nonaligned Support
- 64 General-Purpose Registers (32-Bit)
- Six ALU (32- and 40-Bit) Functional Units
  - Supports 32-Bit Integer, SP (IEEE Single Precision/32-Bit) and DP (IEEE Double Precision/64-Bit) Floating Point
  - Supports up to Four SP Additions Per Clock, Four DP Additions Every 2 Clocks
  - Supports up to Two Floating-Point (SP or DP) Reciprocal Approximation (RCPxP) and Square-Root Reciprocal Approximation (RSQRxP) Operations Per Cycle
- Two Multiply Functional Units
  - Mixed-Precision IEEE Floating Point Multiply Supported up to:
    - 2 SP x SP -> SP Per Clock
    - 2 SP x SP -> DP Every Two Clocks
    - 2 SP x DP -> DP Every Three Clocks
    - 2 DP x DP -> DP Every Four Clocks
  - Fixed-Point Multiply Supports Two 32 x 32-Bit Multiplies, Four 16 x 16-Bit Multiplies, or Eight 8 x 8-Bit Multiplies per Clock Cycle, and Complex Multiples
- Instruction Packing Reduces Code Size
- All Instructions Conditional
- Hardware Support for Modulo Loop
  Operation
- Protected Mode Operation
- Exceptions Support for Error Detection and Program Redirection
128KB of RAM Shared Memory (TMS320C6747 Only)
3.3-V LVCMOS I/Os (Except for USB Interfaces)
Two External Memory Interfaces:
- EMIFA
  - NOR (8- or 16-Bit-Wide Data)
  - NAND (8- or 16-Bit-Wide Data)
  - 16-Bit SDRAM with 128-MB Address Space (TMS320C6747 Only)
- EMIFB
  - 32-Bit or 16-Bit SDRAM with 256-MB Address Space (TMS320C6747)
  - 16-Bit SDRAM with 128-MB Address Space (TMS320C6745)
Three Configurable 16550-Type UART Modules:
- UART0 with Modem Control Signals
- Autoflow Control Signals (CTS, RTS) on UART0 Only
- 16-Byte FIFO
- 16x or 13x Oversampling Option
LCD Controller (TMS320C6747 Only)
Two Serial Peripheral Interfaces (SPIs) Each with One Chip Select
Multimedia Card (MMC)/Secure Digital (SD) Card Interface with Secure Data I/O (SDIO)
Two Master and Slave Inter-Integrated Circuit (I²C Bus™)
One Host-Port Interface (HPI) with 16-Bit-Wide Muxed Address/Data Bus for High Bandwidth (TMS320C6747 Only)
Programmable Real-Time Unit Subsystem (PRUSS)
- Two Independent Programmable Realtime Unit (PRU) Cores
  - 32-Bit Load and Store RISC Architecture
  - 4KB of Instruction RAM per Core
  - 512 Bytes of Data RAM per Core
  - PRUSS can be Disabled via Software to Save Power
- Standard Power-Management Mechanism
  - Clock Gating
  - Entire Subsystem Under a Single PSC Clock Gating Domain
- Dedicated Interrupt Controller
- Dedicated Switched Central Resource
USB 1.1 OHCI (Host) with Integrated PHY (USB1) (TMS320C6747 Only)
USB 2.0 OTG Port with Integrated PHY (USB0)
- USB 2.0 High- and Full-Speed Client (TMS320C6747)
- USB 2.0 Full-Speed Client (TMS320C6745)
- USB 2.0 High-, Full-, and Low-Speed Host (TMS320C6747)
- USB 2.0 Full- and Low-Speed Host (TMS320C6745)
- High-Speed Functionality Available on TMS320C6747 Device Only
- End Point 0 (Control)
- End Points 1,2,3,4 (Control, Bulk, Interrupt or ISOC) RX and TX
Three Multichannel Audio Serial Ports (McASPs):
- TMS320C6747 Supports 3 McASPs
- TMS320C6745 Supports 2 McASPs
- Six Clock Zones and 28 Serial Data Pins
- Supports TDM, I2S, and Similar Formats
- DIT-Capable (McASP2)
- FIFO Buffers for Transmit and Receive
10/100 Mbps Ethernet MAC (EMAC):
- IEEE 802.3 Compliant (3.3-V I/O Only)
- RMII Media-Independent Interface
- Management Data I/O (MDIO) Module
Real-Time Clock with 32-kHz Oscillator and Separate Power Rail (TMS320C6747 Only)
One 64-Bit General-Purpose Timer (Configurable as Two 32-Bit Timers)
One 64-Bit General-Purpose Watchdog Timer (Configurable as Two 32-Bit General-Purpose Timers)
Three Enhanced Pulse Width Modulators (eHRPWMs):
- Dedicated 16-Bit Time-Base Counter with Period and Frequency Control
- 6 Single Edge, 6 Dual Edge Symmetric, or 3 Dual Edge Asymmetric Outputs
- Dead-Band Generation
- PWM Chopping by High-Frequency Carrier
- Trip Zone Input
Three 32-Bit Enhanced Capture (eCAP) Modules:
- Configurable as 3 Capture Inputs or 3 Auxiliary Pulse Width Modulator (APWM) Outputs
- Single-Shot Capture of up to Four Event Time-Stamps
Two 32-Bit Enhanced Quadrature Encoder Pulse (eQEP) Modules
TMS320C6747 Device:
- 256-Ball Pb-Free Plastic Ball Grid Array (PBGA) [ZKB Suffix], 1.0-mm Ball Pitch
TMS320C6745 Device:
- 176-pin PowerPAD™ Plastic Quad Flat Pack [PTP suffix], 0.5-mm Pin Pitch
Commercial, Industrial, Extended, or Automotive Temperature

Software Support
- TI DSP/BIOS™
- Chip Support Library and DSP Library
375- and 456-MHz TMS320C674x VLIW DSP
C674x Instruction Set Features
- Superset of the C67x+ and C64x+ ISAs
- Up to 3648 MIPS and 2736 MFLOPS C674x
- Byte-Addressable (8-, 16-, 32-, and 64-Bit Data)
- 8-Bit Overflow Protection
- Bit-Field Extract, Set, Clear
- Normalization, Saturation, Bit-Counting
- Compact 16-Bit Instructions
C674x Two-Level Cache Memory Architecture
- 32KB of L1P Program RAM/Cache
- 32KB of L1D Data RAM/Cache
- 256KB of L2 Unified Mapped RAM/Cache
- Flexible RAM/Cache Partition (L1 and L2)
Enhanced Direct Memory Access Controller 3 (EDMA3):
- 2 Transfer Controllers
- 32 Independent DMA Channels
- 8 Quick DMA Channels
- Programmable Transfer Burst Size
TMS320C674x Fixed- and Floating-Point VLIW DSP Core
- Load-Store Architecture with Nonaligned Support
- 64 General-Purpose Registers (32-Bit)
- Six ALU (32- and 40-Bit) Functional Units
  - Supports 32-Bit Integer, SP (IEEE Single Precision/32-Bit) and DP (IEEE Double Precision/64-Bit) Floating Point
  - Supports up to Four SP Additions Per Clock, Four DP Additions Every 2 Clocks
  - Supports up to Two Floating-Point (SP or DP) Reciprocal Approximation (RCPxP) and Square-Root Reciprocal Approximation (RSQRxP) Operations Per Cycle
- Two Multiply Functional Units
  - Mixed-Precision IEEE Floating Point Multiply Supported up to:
    - 2 SP x SP -> SP Per Clock
    - 2 SP x SP -> DP Every Two Clocks
    - 2 SP x DP -> DP Every Three Clocks
    - 2 DP x DP -> DP Every Four Clocks
  - Fixed-Point Multiply Supports Two 32 x 32-Bit Multiplies, Four 16 x 16-Bit Multiplies, or Eight 8 x 8-Bit Multiplies per Clock Cycle, and Complex Multiples
- Instruction Packing Reduces Code Size
- All Instructions Conditional
- Hardware Support for Modulo Loop
  Operation
- Protected Mode Operation
- Exceptions Support for Error Detection and Program Redirection
128KB of RAM Shared Memory (TMS320C6747 Only)
3.3-V LVCMOS I/Os (Except for USB Interfaces)
Two External Memory Interfaces:
- EMIFA
  - NOR (8- or 16-Bit-Wide Data)
  - NAND (8- or 16-Bit-Wide Data)
  - 16-Bit SDRAM with 128-MB Address Space (TMS320C6747 Only)
- EMIFB
  - 32-Bit or 16-Bit SDRAM with 256-MB Address Space (TMS320C6747)
  - 16-Bit SDRAM with 128-MB Address Space (TMS320C6745)
Three Configurable 16550-Type UART Modules:
- UART0 with Modem Control Signals
- Autoflow Control Signals (CTS, RTS) on UART0 Only
- 16-Byte FIFO
- 16x or 13x Oversampling Option
LCD Controller (TMS320C6747 Only)
Two Serial Peripheral Interfaces (SPIs) Each with One Chip Select
Multimedia Card (MMC)/Secure Digital (SD) Card Interface with Secure Data I/O (SDIO)
Two Master and Slave Inter-Integrated Circuit (I²C Bus™)
One Host-Port Interface (HPI) with 16-Bit-Wide Muxed Address/Data Bus for High Bandwidth (TMS320C6747 Only)
Programmable Real-Time Unit Subsystem (PRUSS)
- Two Independent Programmable Realtime Unit (PRU) Cores
  - 32-Bit Load and Store RISC Architecture
  - 4KB of Instruction RAM per Core
  - 512 Bytes of Data RAM per Core
  - PRUSS can be Disabled via Software to Save Power
- Standard Power-Management Mechanism
  - Clock Gating
  - Entire Subsystem Under a Single PSC Clock Gating Domain
- Dedicated Interrupt Controller
- Dedicated Switched Central Resource
USB 1.1 OHCI (Host) with Integrated PHY (USB1) (TMS320C6747 Only)
USB 2.0 OTG Port with Integrated PHY (USB0)
- USB 2.0 High- and Full-Speed Client (TMS320C6747)
- USB 2.0 Full-Speed Client (TMS320C6745)
- USB 2.0 High-, Full-, and Low-Speed Host (TMS320C6747)
- USB 2.0 Full- and Low-Speed Host (TMS320C6745)
- High-Speed Functionality Available on TMS320C6747 Device Only
- End Point 0 (Control)
- End Points 1,2,3,4 (Control, Bulk, Interrupt or ISOC) RX and TX
Three Multichannel Audio Serial Ports (McASPs):
- TMS320C6747 Supports 3 McASPs
- TMS320C6745 Supports 2 McASPs
- Six Clock Zones and 28 Serial Data Pins
- Supports TDM, I2S, and Similar Formats
- DIT-Capable (McASP2)
- FIFO Buffers for Transmit and Receive
10/100 Mbps Ethernet MAC (EMAC):
- IEEE 802.3 Compliant (3.3-V I/O Only)
- RMII Media-Independent Interface
- Management Data I/O (MDIO) Module
Real-Time Clock with 32-kHz Oscillator and Separate Power Rail (TMS320C6747 Only)
One 64-Bit General-Purpose Timer (Configurable as Two 32-Bit Timers)
One 64-Bit General-Purpose Watchdog Timer (Configurable as Two 32-Bit General-Purpose Timers)
Three Enhanced Pulse Width Modulators (eHRPWMs):
- Dedicated 16-Bit Time-Base Counter with Period and Frequency Control
- 6 Single Edge, 6 Dual Edge Symmetric, or 3 Dual Edge Asymmetric Outputs
- Dead-Band Generation
- PWM Chopping by High-Frequency Carrier
- Trip Zone Input
Three 32-Bit Enhanced Capture (eCAP) Modules:
- Configurable as 3 Capture Inputs or 3 Auxiliary Pulse Width Modulator (APWM) Outputs
- Single-Shot Capture of up to Four Event Time-Stamps
Two 32-Bit Enhanced Quadrature Encoder Pulse (eQEP) Modules
TMS320C6747 Device:
- 256-Ball Pb-Free Plastic Ball Grid Array (PBGA) [ZKB Suffix], 1.0-mm Ball Pitch
TMS320C6745 Device:
- 176-pin PowerPAD™ Plastic Quad Flat Pack [PTP suffix], 0.5-mm Pin Pitch
Commercial, Industrial, Extended, or Automotive Temperature

The TMS320C6745/6747 device is a low-power digital signal processor based on a TMS320C674x DSP core. It consumes significantly lower power than other members of the TMS320C6000™ platform of DSPs.

The TMS320C6745/6747 device enables original-equipment manufacturers (OEMs) and original-design manufacturers (ODMs) to quickly bring to market devices featuring high processing performance .

The TMS320C6745/6747 DSP core uses a two-level cache-based architecture. The Level 1 program cache (L1P) is a 32-KB direct mapped cache and the Level 1 data cache (L1D) is a 32-KB 2-way set-associative cache. The Level 2 program cache (L2P) consists of a 256-KB memory space that is shared between program and data space. L2 memory can be configured as mapped memory, cache, or combinations of the two. Although the DSP L2 is accessible by other hosts in the system, an additional 128KB of RAM shared memory (TMS320C6747 only) is available for use by other hosts without affecting DSP performance.

The peripheral set includes: a 10/100 Mbps Ethernet MAC (EMAC) with a management data input/output (MDIO) module; two I²C Bus interfaces; 3 multichannel audio serial ports (McASPs) with 16/9 serializers and FIFO buffers; two 64-bit general-purpose timers each configurable (one configurable as watchdog); a configurable 16-bit host-port interface (HPI) [TMS320C6747 only]; up to 8 banks of 16 pins of general-purpose input/output (GPIO) with programmable interrupt/event generation modes, multiplexed with other peripherals; 3 UART interfaces (one with both RTS and CTS); three enhanced high-resolution pulse width modulator (eHRPWM) peripherals; three 32-bit enhanced capture (eCAP) module peripherals which can be configured as 3 capture inputs or 3 auxiliary pulse width modulator (APWM) outputs; two 32-bit enhanced quadrature encoded pulse (eQEP) peripherals; and 2 external memory interfaces: an asynchronous and SDRAM external memory interface (EMIFA) for slower memories or peripherals, and a higher speed memory interface (EMIFB) for SDRAM.

The Ethernet Media Access Controller (EMAC) provides an efficient interface between the TMS320C6745/6747 device and the network. The EMAC supports both 10Base-T and 100Base-TX, or 10 Mbps and 100 Mbps in either half- or full-duplex mode. Additionally, an MDIO interface is available for PHY configuration.

The rich peripheral set provides the ability to control external peripheral devices and communicate with external processors. For details on each of the peripherals, see the related sections later in this document and the associated peripheral reference guides.

The TMS320C6745/6747 device is a low-power digital signal processor based on a TMS320C674x DSP core. It consumes significantly lower power than other members of the TMS320C6000™ platform of DSPs.

The TMS320C6745/6747 device enables original-equipment manufacturers (OEMs) and original-design manufacturers (ODMs) to quickly bring to market devices featuring high processing performance .

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Documentación técnica

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	Tipo	Título		Fecha
*	Data sheet	TMS320C6745, TMS320C6747 Fixed- and Floating-Point Digital Signal Processor datasheet (Rev. F)	PDF \| HTML	17 jun 2014
*	Errata	TMS320C6747 Fixed/Floating-Point DSP SE (Silicon Revs 3.0, 2.1, 2.0, 1.1, & 1.0) (Rev. G)		17 jun 2014
*	User guide	TMS320C6745/C6747 DSP Technical Reference Manual (Rev. D)		21 sep 2016
	Application note	How to Migrate CCS 3.x Projects to the Latest CCS (Rev. A)	PDF \| HTML	19 may 2021
	User guide	SYS/BIOS (TI-RTOS Kernel) User's Guide (Rev. V)		01 jun 2020
	Application note	Using DSPLIB FFT Implementation for Real Input and Without Data Scaling	PDF \| HTML	11 jun 2019
	Application note	Programming PLL Controllers on OMAP-L1x8/C674x/AM18xx		25 abr 2019
	Application note	TMS320C6747/45/43 Power Consumption Summary		23 abr 2019
	Application note	General Hardware Design/BGA PCB Design/BGA		22 feb 2019
	Application note	OMAP-L13x / C674x / AM1x schematic review guidelines	PDF \| HTML	14 feb 2019
	Application note	McASP Design Guide - Tips, Tricks, and Practical Examples		10 ene 2019
	White paper	Designing professional audio mixers for every scenario		28 jun 2018
	White paper	Voice as the user interface – a new era in speech processing white Paper		09 may 2017
	Application note	Processor SDK RTOS Audio Benchmark Starter Kit		12 abr 2017
	User guide	OMAP-L137 C6000 DSP+ARM Processor Technical Reference Manual (Rev. D)		21 sep 2016
	Application note	Plastic Ball Grid Array [PBGA] Application Note (Rev. B)		13 ago 2015
	User guide	System Analyzer User's Guide (Rev. F)		18 nov 2013
	Application note	Using the OMAP-L1x7 Bootloader (Rev. G)		01 jun 2012
	Application note	Using the TMS320C6747/45/43 Bootloader (Rev. C)		01 jun 2012
	Application note	Powering the TMS320C6745 and TMS320C6747 with the TPS650061		25 oct 2011
	Application note	Introduction to TMS320C6000 DSP Optimization		06 oct 2011
	User guide	TMS320C674x/OMAP-L1x Processor Peripherals Overview Reference Guide (Rev. F)		14 sep 2011
	White paper	Software and Hardware Design Challenges Due to Dynamic Raw NAND Market		19 may 2011
	Application note	Power Solution Using Discrete DC/DC Converters and LDOs (Rev. B)		26 ago 2010
	User guide	TMS320C674x DSP Megamodule Reference Guide (Rev. A)		03 ago 2010
	User guide	TMS320C674x DSP CPU and Instruction Set User's Guide (Rev. B)		30 jul 2010
	Application note	Power Solution using LDO's (Rev. A)		25 mar 2010
	Application note	Power Solution using a Dual DCDC Converter and a LDO (Rev. A)		25 mar 2010
	Application note	OMAP-L137 TMS320C6747/6745/6743 Pin Multiplexing Utility (Rev. A)		26 sep 2009
	Application note	TMS320C6747/45/43 Complementary Products		23 sep 2009
	White paper	Efficient Fixed- and Floating-Point Code Execution on the TMS320C674x Core		24 jun 2009
	Product overview	TMS320C674x Product Bulletin (Rev. B)		08 abr 2009
	Application note	TMS320C6747/45/43 & OMAP-L1x7 USB Downstream Host Compliance Testing		12 mar 2009
	Application note	TMS320C6747/45/43 & OMAP-L1x7 USB Upstream Device Compliance Testing		12 mar 2009
	Application note	TMS320C674x/OMAP-L1x USB Compliance Checklist		12 mar 2009
	Application note	TMS320C6747 Technical Brief (Rev. B)		18 feb 2009
	User guide	TMS320C674x DSP Cache User's Guide (Rev. A)		11 feb 2009

Diseño y desarrollo

Para conocer los términos adicionales o los recursos necesarios, haga clic en cualquier título de abajo para ver la página de detalles cuando esté disponible.

Placa de evaluación

TMDSOSKL137 — Kit básico de punto flotante OMAP-L137/TMS320C6747

The OMAP-L137/TMS320C6747 Floating-Point Starter Kit, developed jointly with Spectrum Digital Inc., is a low-cost development platform designed to speed the development of high-precision applications based on TI's OMAP-L13x applications processors and TMS320C674x fixed-/floating-point DSPs (...)

No disponible en TI.com

Sonda de depuración

TMDSEMU200-U — Sonda de depuración XDS200 USB

The XDS200 is a debug probe (emulator) used for debugging TI embedded devices. For the majority of devices it is recommended to use the newer, lower cost XDS110 (www.ti.com/tool/TMDSEMU110-U). The XDS200 supports a wide variety of standards (IEEE1149.1, IEEE1149.7, SWD) in a single pod. All XDS (...)

No disponible en TI.com

Sonda de depuración

TMDSEMU560V2STM-U — Sonda de depuración USB de seguimiento del sistema XDS560v2

The XDS560v2 is the highest performance of the XDS560™ family of debug probes and supports both the traditional JTAG standard (IEEE1149.1) and cJTAG (IEEE1149.7). Note that it does not support serial wire debug (SWD).

All XDS debug probes support Core and System Trace in all ARM and DSP processors (...)

No disponible en TI.com

Sonda de depuración

TMDSEMU560V2STM-UE — Sonda de depuración USB y ethernet de seguimiento del sistema XDS560v2

All XDS debug probes support Core and System Trace in all ARM and DSP processors (...)

No disponible en TI.com

Sonda de depuración

LB-3P-TRACE32-DSP — Sistema de depuración y seguimiento Lauterbach TRACE32 para procesadores de señales digitales (DSP)

Lauterbach‘s TRACE32® tools are a suite of leading-edge hardware and software components that enables developers to analyze, optimize and certify all kinds of single- or multi-core Digital Signal processors (DSPs) which are a popular choice for audio and video processing as well as radar data (...)

Desde: Lauterbach GmbH

View Options

Kit de desarrollo de software (SDK)

PROCESSOR-SDK-C6747 — SDK de procesador para procesadores C6747: Compatibilidad con TI-RTOS

El procesador de kit de desarrollo de software (SDK) es una plataforma de software unificada para procesadores integrados de TI que ofrece una configuración sencilla y un rápido acceso inmediato a pruebas de rendimiento y demostraciones. Todas las versiones del SDK del procesador son coherentes (...)

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Controlador o biblioteca

AEC-AER — Acoustic echo cancellation/removal for TI C64x+, C674x, C55x and Cortex®-A8 processors

Voice Library - VoLIB provides components that, together, facilitate the development of the signal processing chain for Voice over IP applications such as infrastructure, enterprise, residential gateways and IP phones. Together with optimized implementations of ITU-T voice codecs, that can be (...)

Productos y hardware compatibles

Productos

SoC del procesador de señal digital (DSP) de radar y audio

66AK2G12 — DSP+Arm multinúcleo de alto rendimiento: 1x Arm, núcleos A15, 1x C66x DSP núcleo

DM505 — SOC para análisis de visión en paquete de 15 mm

SM320C6201-EP — DSP de punto fijo C6201 de producto mejorado

SM320C6415-EP — DSP de punto fijo C6415 de producto mejorado

SM320C6424-EP — DSP de punto fijo C6424 de producto mejorado

SM320C6455-EP — DSP de punto fijo C6455 de producto mejorado

SM320C6472-HIREL — DSP de punto fijo C6472 de 6 núcleos de producto de alta confiabilidad

SM320C6678-HIREL — DSP de punto flotante y fijo C6678 de 8 núcleos de alto rendimiento y de producto de alta confiabili

SM320C6701 — DSP de punto flotante C67x de núcleo único para aplicaciones militares, de hasta 167 MHz

SM320C6701-EP — DSP de punto flotante C6701 de producto mejorado

SM320C6711D-EP — DSP de punto flotante C6711D de producto mejorado

SM320C6712D-EP — DSP C6712D de producto mejorado

SM320C6713B-EP — DSP de punto flotante C6713 de producto mejorado

SM320C6727B — DSP de punto flotante de calidad militar C6727B

SM320C6727B-EP — DSP de punto flotante C6727 de producto mejorado

SMJ320C6201B — Procesador de señal digital de punto fijo, de calidad militar

SMJ320C6203 — DSP de punto fijo de calidad militar C62x: encapsulado cerámico

SMJ320C6415 — DSP de punto fijo de calidad militar C64x: encapsulado cerámico

SMJ320C6701 — DSP de punto flotante de calidad militar C67x: encapsulado cerámico

SMJ320C6701-SP — DSP de punto flotante C6701 grado espacial, clase V tolerante a la radiación con encapsulado cerámic

SMV320C6727B-SP — DSP de punto flotante C6727B grado espacial, clase V tolerante a la radiación con paquete cerámico

TMS320C5517 — DSP de punto fijo C55x de bajo consumo: hasta 200 MHz, USB, interfaz LCD, FFT HWA, SAR ADC

TMS320C5532 — DSP de punto fijo C55x de baja potencia y hasta 100 MHz

TMS320C5533 — DSP de punto fijo C55x de baja potencia y hasta 100 MHz con USB

TMS320C5534 — DSP de punto fijo C55x de baja potencia y hasta 100 MHz, con interfaz LCD

TMS320C5535 — DSP de punto fijo C55x de bajo consumo: hasta 100 MHz, USB, interfaz LCD, FFT HWA, SAR ADC

TMS320C6202B — DSP de punto fijo C62x de hasta 300 MHz y 384 KB

TMS320C6203B — Procesador de señal digital (DSP) de punto fijo C62x de hasta 300 MHz y 896 KB

TMS320C6204 — Procesador de señal digital de punto fijo

TMS320C6205 — Procesador de señal digital de punto fijo

TMS320C6211B — DSP de punto fijo C62x de hasta 167 MHz

TMS320C6414 — DSP de punto fijo C64x de hasta 720 MHz, con McBSP

TMS320C6415 — DSP de punto fijo C64x de hasta 720 MHz, con McBSP y PCI

TMS320C6416 — DSP de punto fijo C64x de hasta 720 MHz, con McBSP, PCI y VCP/TCP

TMS320C6421Q — DSP de punto fijo C64x+ de hasta 600 MHz, EMIFA de 8 bits y DDR2 de 16 bits

TMS320C6424Q — DSP de punto fijo C64x+ de hasta 600 MHz, EMIFA de 16/8 bits y DDR2 de 32/16 bits

TMS320C6454 — DSP de punto fijo C64x+ de hasta 1 GHz, con EMIFA de 64 bits, DDR2 de 32/16 bits y Ethernet de 1 Gbp

TMS320C6457 — Procesador de señal digital de infraestructura de comunicaciones

TMS320C6701 — DSP de punto flotante C67x de hasta 167 MHz, con McBSP

TMS320C6711D — DSP de punto flotante C67x de hasta 250MHz, con McBSP y EMIFA de 32 bits

TMS320C6712D — DSP de punto flotante C67x de hasta 150MHz, con McBSP y EMIFA de 16 bits

TMS320C6720 — DSP de punto flotante C67x de hasta 200 MHz, con McASP y EMIFA de 16 bits

TMS320C6722B — DSP de punto flotante C67x de hasta 250 MHz, con McASP y EMIFA de 16 bits

TMS320C6726B — DSP de punto flotante C67x de hasta 266 MHz, con McASP y EMIFA de 16 bits

TMS320C6727 — DSP de punto flotante C67x de hasta 250 MHz, con McASP y EMIFA de 32 bits

TMS320C6727B — DSP de punto flotante C67x de hasta 350 MHz, con McASP y EMIFA de 32 bits

TMS320C6743 — DSP de punto flotante C674x de 375 MHz y baja potencia

TMS320C6745 — DSP de punto flotante C674x de 456 MHz y baja potencia, con QFP

TMS320C6747 — DSP de punto flotante C674x de 456 MHz y baja potencia, con PBGA

SoC de redes industriales y multimedia

TMS320DM6441 — Sistema en chip de medios digitales DaVinci

TMS320DM6467T — Sistema de medios digitales en chip

TMS320DM647 — Procesador de medios digitales

Sistemas automotrices SoC de asistencia al conductor

TMS320DM642Q — Procesador de señal digital de punto fijo de imágenes y video

TMS320DM6431Q — Procesador de medios digitales de hasta 2,400 MIPS y velocidad de reloj de 300 MHz

TMS320DM6435Q — Procesador de medios digitales, hasta 4.800 MIPS y velocidad de reloj de 600 MHz, 1 McASP y 1 McBSP

TMS320DM6437Q — Procesador de medios digitales de hasta 4800 MIPS, velocidad de reloj de 600 MHz c/ 1 McASP, 2 McBSP

Opciones de descarga

Controlador o biblioteca

C64X-DSPLIB — Download TMS320C64x DSP Library

TMS320C6000 Digital Signal Processor Library (DSPLIB) is a platform-optimized DSP function library for C programmers. It includes C-callable, general-purpose signal-processing routines that are typically used in computationally intensive real-time applications. With these routines, higher (...)