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TPS7H6200-SEP

PRESENTACIÓN PRELIMINAR

Detalles del producto

VDS (max) (V) 17 RDS(on) (mΩ) 1000, 3000 ID (max) (A) 52 Features Half-bridge, Integrated Current Sensing, Integrated bootstrap diode, Over Temperature Protection, current limiting Rating Space Operating temperature range (°C) -55 to 125
VDS (max) (V) 17 RDS(on) (mΩ) 1000, 3000 ID (max) (A) 52 Features Half-bridge, Integrated Current Sensing, Integrated bootstrap diode, Over Temperature Protection, current limiting Rating Space Operating temperature range (°C) -55 to 125
WQFN-FCRLF (VEJ) 49 36 mm² (6 mm × 6 mm)
  • Total ionizing dose (TID) characterized up to 50krad(Si)
  • Destructive Single Event Effects (DSEE) characterized
    • Single-event latchup (SEL), single-event burnout (SEB), and single-event gate rupture (SEGR) immune up to linear energy transfer LET = 43MeV⋅cm2/mg
  • Single Event Effects characterized
    • Single-event functional interrupt (SEFI) and single-event transient (SET) characterized up to LET = 43MeV⋅cm2/mg
  • Available in military (–55°C to 125°C) temperature
  • 3.2mΩ (typ) high side FET RDSON, 1mΩ low side FET RDSON
  • High efficiency (VPVIN = 12V, VVOUT = 0.8V, fSW = 500kHz, TA =25°C, L = 200nH, DCR = 180mΩ):
    • η = 89.6% at 20A
    • η = 87.2% at 40A
    • η = 84.9% at 52A
  • 52A maximum continuous current
  • Integrated low-side current sense
    • Total RSS accuracy of 14.5% for nominal load currents greater than 40A
  • Fault pin indicator for overcurrent, overtemperature, or UVLO detection
  • DrMOS 3.3V and 5V PWM input signal compatibility
  • Integrated overtemperature and overcurrent protection
  • Total ionizing dose (TID) characterized up to 50krad(Si)
  • Destructive Single Event Effects (DSEE) characterized
    • Single-event latchup (SEL), single-event burnout (SEB), and single-event gate rupture (SEGR) immune up to linear energy transfer LET = 43MeV⋅cm2/mg
  • Single Event Effects characterized
    • Single-event functional interrupt (SEFI) and single-event transient (SET) characterized up to LET = 43MeV⋅cm2/mg
  • Available in military (–55°C to 125°C) temperature
  • 3.2mΩ (typ) high side FET RDSON, 1mΩ low side FET RDSON
  • High efficiency (VPVIN = 12V, VVOUT = 0.8V, fSW = 500kHz, TA =25°C, L = 200nH, DCR = 180mΩ):
    • η = 89.6% at 20A
    • η = 87.2% at 40A
    • η = 84.9% at 52A
  • 52A maximum continuous current
  • Integrated low-side current sense
    • Total RSS accuracy of 14.5% for nominal load currents greater than 40A
  • Fault pin indicator for overcurrent, overtemperature, or UVLO detection
  • DrMOS 3.3V and 5V PWM input signal compatibility
  • Integrated overtemperature and overcurrent protection

The TPS7H6200-SEP is a 15V e-mode GaN power-FET with integrated gate driver featuring tri-state PWM compatibility, integrated low side current sense, overtemperature protection, and overcurrent protection.

The GaN FET half-bridge die combines the high-side and low-side GaN FETs on one substrate, minimizing parasitic inductance. The device is asymmetrically sized for point-of-load voltage conversion, 1mΩ on the low side and 3mΩ on the high side, optimizing performance and efficiency for typical input to output conversion ratios. As a result, the TPS7H6200-SEP can achieve efficiencies exceeding 89.6% at a typical load of 20A.

The TPS7H6200-SEP is a 15V e-mode GaN power-FET with integrated gate driver featuring tri-state PWM compatibility, integrated low side current sense, overtemperature protection, and overcurrent protection.

The GaN FET half-bridge die combines the high-side and low-side GaN FETs on one substrate, minimizing parasitic inductance. The device is asymmetrically sized for point-of-load voltage conversion, 1mΩ on the low side and 3mΩ on the high side, optimizing performance and efficiency for typical input to output conversion ratios. As a result, the TPS7H6200-SEP can achieve efficiencies exceeding 89.6% at a typical load of 20A.

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* Hoja de datos TPS7H6200-SEP Radiation-Tolerant 52A GaN Half-Bridge Power Stage with Low-Side Current Sense datasheet PDF | HTML 23/09/2026

Diseño y desarrollo

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Placa de evaluación

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