ADC12L066

アクティブ

12 ビット、66MSPS、450MHz の入力帯域幅、A/D コンバータ (ADC)

製品詳細

Sample rate (max) (Msps) 66 Resolution (Bits) 12 Number of input channels 1 Interface type Parallel CMOS, TTL Analog input BW (MHz) 450 Features Low Power Rating Catalog Peak-to-peak input voltage range (V) 2 Power consumption (typ) (mW) 357 Architecture Pipeline SNR (dB) 66 ENOB (Bits) 10.7 SFDR (dB) 80 Operating temperature range (°C) -40 to 85 Input buffer No
Sample rate (max) (Msps) 66 Resolution (Bits) 12 Number of input channels 1 Interface type Parallel CMOS, TTL Analog input BW (MHz) 450 Features Low Power Rating Catalog Peak-to-peak input voltage range (V) 2 Power consumption (typ) (mW) 357 Architecture Pipeline SNR (dB) 66 ENOB (Bits) 10.7 SFDR (dB) 80 Operating temperature range (°C) -40 to 85 Input buffer No
LQFP (NEY) 32 81 mm² (9 mm × 9 mm)
  • Single Supply Operation
  • Low Power Consumption
  • Power Down Mode
  • On-Chip Reference Buffer

Key Specifications

  • Resolution: 12 Bits
  • Conversion Rate: 66 Msps
  • Full Power Bandwidth: 450 MHz
  • DNL: ±0.4 LSB (typ)
  • SNR (fIN = 10 MHz): 66 dB (typ)
  • SFDR (fIN = 10 MHz): 80 dB (typ)
  • Data Latency: 6 Clock Cycles
  • Supply Voltage: +3.3V ± 300 mV
  • Power Consumption, 66 MHz: 357 mW (typ)

All trademarks are the property of their respective owners. TRI-STATE is a trademark of Texas Instruments.

  • Single Supply Operation
  • Low Power Consumption
  • Power Down Mode
  • On-Chip Reference Buffer

Key Specifications

  • Resolution: 12 Bits
  • Conversion Rate: 66 Msps
  • Full Power Bandwidth: 450 MHz
  • DNL: ±0.4 LSB (typ)
  • SNR (fIN = 10 MHz): 66 dB (typ)
  • SFDR (fIN = 10 MHz): 80 dB (typ)
  • Data Latency: 6 Clock Cycles
  • Supply Voltage: +3.3V ± 300 mV
  • Power Consumption, 66 MHz: 357 mW (typ)

All trademarks are the property of their respective owners. TRI-STATE is a trademark of Texas Instruments.

The ADC12L066 is a monolithic CMOS analog-to-digital converter capable of converting analog input signals into 12-bit digital words at 66 Megasamples per second (Msps), minimum, with typical operation possible up to 80 Msps. This converter uses a differential, pipeline architecture with digital error correction and an on-chip sample-and-hold circuit to minimize die size and power consumption while providing excellent dynamic performance. A unique sample-and-hold stage yields a full-power bandwidth of 450 MHz. Operating on a single 3.3V power supply, this device consumes just 357 mW at 66 Msps, including the reference current. The Power Down feature reduces power consumption to just 50 mW.

The differential inputs provide a full scale input swing equal to ±VREF with the possibility of a single-ended input. Full use of the differential input is recommended for optimum performance. For ease of use, the buffered, high impedance, single-ended reference input is converted on-chip to a differential reference for use by the processing circuitry. Output data format is 12-bit offset binary.

This device is available in the 32-lead LQFP package and will operate over the industrial temperature range of −40°C to +85°C. An evaluation board is available to facilitate the evaluation process.

The ADC12L066 is a monolithic CMOS analog-to-digital converter capable of converting analog input signals into 12-bit digital words at 66 Megasamples per second (Msps), minimum, with typical operation possible up to 80 Msps. This converter uses a differential, pipeline architecture with digital error correction and an on-chip sample-and-hold circuit to minimize die size and power consumption while providing excellent dynamic performance. A unique sample-and-hold stage yields a full-power bandwidth of 450 MHz. Operating on a single 3.3V power supply, this device consumes just 357 mW at 66 Msps, including the reference current. The Power Down feature reduces power consumption to just 50 mW.

The differential inputs provide a full scale input swing equal to ±VREF with the possibility of a single-ended input. Full use of the differential input is recommended for optimum performance. For ease of use, the buffered, high impedance, single-ended reference input is converted on-chip to a differential reference for use by the processing circuitry. Output data format is 12-bit offset binary.

This device is available in the 32-lead LQFP package and will operate over the industrial temperature range of −40°C to +85°C. An evaluation board is available to facilitate the evaluation process.

ダウンロード 字幕付きのビデオを表示 ビデオ

技術資料

結果が見つかりませんでした。検索条件をクリアしてから、再度検索を試してください。
1 をすべて表示
上位の文書 タイプ タイトル フォーマットオプション 最新の英語版をダウンロード 日付
* データシート ADC12L066 12-Bit, 66 MSPS, 450 MHz Bandwidth ADC w/Internal Sample-and-Hold データシート (Rev. I) 2013/03/14

設計と開発

その他のアイテムや必要なリソースを参照するには、以下のタイトルをクリックして詳細ページをご覧ください。

パッケージ ピン数 CAD シンボル、フットプリント、および 3D モデル
LQFP (NEY) 32 Ultra Librarian

購入と品質

推奨製品には、この TI 製品に関連するパラメータ、評価基板、またはリファレンス デザインが存在する可能性があります。

サポートとトレーニング

TI E2E™ フォーラムでは、TI のエンジニアからの技術サポートを提供

コンテンツは、TI 投稿者やコミュニティ投稿者によって「現状のまま」提供されるもので、TI による仕様の追加を意図するものではありません。使用条件をご確認ください。

TI 製品の品質、パッケージ、ご注文に関するお問い合わせは、TI サポートをご覧ください。​​​​​​​​​​​​​​

ビデオ