홈 데이터 컨버터 아날로그-디지털 컨버터(ADC) 고속 ADC(≥10 MSPS)
홈
데이터 컨버터
아날로그-디지털 컨버터(ADC)
고속 ADC(≥10 MSPS)

ADC12DL3200

활성

12비트, 듀얼 3.2GSPS 또는 단일 6.4GSPS, RF 샘플링 아날로그-디지털 컨버터(LVDS 인터페이스)

지금 주문하기
데이터 시트

ADC12DL3200

활성
데이터 시트 지금 주문하기

제품 상세 정보

Sample rate (max) (Msps) 3200, 6400 Resolution (Bits) 12 Number of input channels 1, 2 Interface type DDR LVDS, Parallel LVDS Analog input BW (MHz) 8000 Features Ultra High Speed Rating Catalog Peak-to-peak input voltage range (V) 0.8 Power consumption (typ) (mW) 3150 Architecture Folding Interpolating SNR (dB) 57.9 ENOB (Bits) 9 SFDR (dB) 78 Operating temperature range (°C) -40 to 85 Input buffer Yes
Sample rate (max) (Msps) 3200, 6400 Resolution (Bits) 12 Number of input channels 1, 2 Interface type DDR LVDS, Parallel LVDS Analog input BW (MHz) 8000 Features Ultra High Speed Rating Catalog Peak-to-peak input voltage range (V) 0.8 Power consumption (typ) (mW) 3150 Architecture Folding Interpolating SNR (dB) 57.9 ENOB (Bits) 9 SFDR (dB) 78 Operating temperature range (°C) -40 to 85 Input buffer Yes
FCBGA (ACF) 256 289 mm² (0 mm × 0 mm) FCBGA (ALJ) 256 289 mm² (17 mm × 17 mm)
  • ADC Core:
    • 12-Bit Resolution
    • Up to 6.4 GSPS in Single-Channel Mode
    • Up to 3.2 GSPS in Dual-Channel Mode
  • Internal Dither for Low-Magnitude, High-Order Harmonics
  • Low-Latency LVDS Interface:
    • Total Latency: < 10 ns
    • Up to 48 Data Pairs at 1.6 Gbps
    • Four DDR Data Clocks
    • Strobe Signals Simplify Synchronization
  • Noise Floor (No Input, V FS = 1.0 V PP-DIFF):
    • Dual-Channel Mode: –151.1 dBFS/Hz
    • Single-Channel Mode: –154.3 dBFS/Hz
  • Buffered Analog Inputs With V CMI of 0 V:
    • Analog Input Bandwidth (–3 dB): 8.0 GHz
    • Usable Input Frequency Range: > 10 GHz
    • Full-Scale Input Voltage (V FS, Default): 0.8 V PP
  • Noiseless Aperture Delay (T AD) Adjustment:
    • Precise Sampling Control: 19-fs Step
    • Simplifies Synchronization and Interleaving
    • Temperature and Voltage Invariant Delays
  • Easy-to-Use Synchronization Features:
    • Automatic SYSREF Timing Calibration
    • Timestamp for Sample Marking
  • Power Consumption: 3.15 W
  • ADC Core:
    • 12-Bit Resolution
    • Up to 6.4 GSPS in Single-Channel Mode
    • Up to 3.2 GSPS in Dual-Channel Mode
  • Internal Dither for Low-Magnitude, High-Order Harmonics
  • Low-Latency LVDS Interface:
    • Total Latency: < 10 ns
    • Up to 48 Data Pairs at 1.6 Gbps
    • Four DDR Data Clocks
    • Strobe Signals Simplify Synchronization
  • Noise Floor (No Input, V FS = 1.0 V PP-DIFF):
    • Dual-Channel Mode: –151.1 dBFS/Hz
    • Single-Channel Mode: –154.3 dBFS/Hz
  • Buffered Analog Inputs With V CMI of 0 V:
    • Analog Input Bandwidth (–3 dB): 8.0 GHz
    • Usable Input Frequency Range: > 10 GHz
    • Full-Scale Input Voltage (V FS, Default): 0.8 V PP
  • Noiseless Aperture Delay (T AD) Adjustment:
    • Precise Sampling Control: 19-fs Step
    • Simplifies Synchronization and Interleaving
    • Temperature and Voltage Invariant Delays
  • Easy-to-Use Synchronization Features:
    • Automatic SYSREF Timing Calibration
    • Timestamp for Sample Marking
  • Power Consumption: 3.15 W

The ADC12DL3200 is an RF-sampling, giga-sample, analog-to-digital converter (ADC) that can directly sample input frequencies from DC to above 10 GHz. In dual-channel mode, the ADC12DL3200 can sample up to 3200 MSPS and in single-channel mode up to 6400 MSPS. Programmable tradeoffs in channel count (dual-channel mode) and Nyquist bandwidth (single-channel mode) allow development of flexible hardware that meets the needs of both high-channel count or wide instantaneous signal bandwidth applications. Full-power input bandwidth (–3 dB) of 8.0 GHz and a useable frequency range allows direct RF sampling of L-band, S-band, C-band, and X-band for frequency agile systems.

The ADC12DL3200 uses a low-latency, low-voltage differential signaling (LVDS) interface for latency sensitive applications or when the simplicity of LVDS is preferred. The interface uses up to 48 data pairs, four double data rate (DDR) clocks, and four strobe signals arranged in four 12-bit data buses. The interface supports signaling rates of up to 1.6 Gbps. Strobe signals simplify synchronization across buses and between multiple devices. The strobe is generated internally and can be reset at a deterministic time by the SYSREF input. Multi-device synchronization is further eased by innovative synchronization features such as noiseless aperture delay (T AD) adjustment and SYSREF windowing.

The ADC12DL3200 is an RF-sampling, giga-sample, analog-to-digital converter (ADC) that can directly sample input frequencies from DC to above 10 GHz. In dual-channel mode, the ADC12DL3200 can sample up to 3200 MSPS and in single-channel mode up to 6400 MSPS. Programmable tradeoffs in channel count (dual-channel mode) and Nyquist bandwidth (single-channel mode) allow development of flexible hardware that meets the needs of both high-channel count or wide instantaneous signal bandwidth applications. Full-power input bandwidth (–3 dB) of 8.0 GHz and a useable frequency range allows direct RF sampling of L-band, S-band, C-band, and X-band for frequency agile systems.

The ADC12DL3200 uses a low-latency, low-voltage differential signaling (LVDS) interface for latency sensitive applications or when the simplicity of LVDS is preferred. The interface uses up to 48 data pairs, four double data rate (DDR) clocks, and four strobe signals arranged in four 12-bit data buses. The interface supports signaling rates of up to 1.6 Gbps. Strobe signals simplify synchronization across buses and between multiple devices. The strobe is generated internally and can be reset at a deterministic time by the SYSREF input. Multi-device synchronization is further eased by innovative synchronization features such as noiseless aperture delay (T AD) adjustment and SYSREF windowing.
filter 기타 고속 ADC(≥10 MSPS) 찾기
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기술 자료

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2개 모두 보기
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* 데이터 시트 ADC12DL3200 6.4-GSPS Single-Channel or 3.2-GSPS Dual-Channel, 12-Bit Analog-to-Digital Converter (ADC) With LVDS Interface datasheet (Rev. C) PDF | HTML 2023. 5. 23
기술 문서 So, what are S-parameters anyway? PDF | HTML 2019. 5. 23

설계 및 개발

추가 조건 또는 필수 리소스는 사용 가능한 경우 아래 제목을 클릭하여 세부 정보 페이지를 확인하세요.

평가 보드

ADC12DL3200EVM — ADC12DL3200 12비트, 듀얼 3.2GSPS 또는 싱글 6.4GSPS, RF 샘플링 ADC 평가 모듈

ADC12DJ3200 EVM(평가 모듈)은 ADC12DJ3200 고속 ADC(아날로그-디지털 컨버터)를 평가하도록 설계되었습니다. EVM에는 LVDS 인터페이스를 지원하는 12비트, 듀얼 채널 3.2GSPS 또는 싱글 채널 6.4GSPS ADC인 ADC12DJ3200이 장착되어 있습니다.
사용 설명서: PDF | HTML
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펌웨어

SLVC814 — TSW14DL3200 ADC12DL3200 Reference Design Firmware

지원되는 제품 및 하드웨어
평가 모듈(EVM)용 GUI

SLVC719 — ADC12DLxx00EVM GUI

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플러그 인

ABACO-3P-FMC172 — Abaco Systems® 광대역 저지연 고속 ADC/DAC 모듈 메자닌 카드

Abaco FMC172 모듈에는 FMC(FPGA 메자닌 카드) 커넥터가 탑재된 도터카드에 텍사스 인스트루먼트의 저지연 ADC12DL3200 1채널 6.4GSPS ADC(아날로그-디지털 컨버터)가 장착되어 있습니다. FMC172의 6GHz 초과 대역폭, 높은 샘플 레이트 및 낮은 지연 시간 특성은 고급 DRFM(디지털 RF 메모리) 시스템에 이상적입니다.

발송: Abaco Systems
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시뮬레이션 모델

ADC12DL3200 IBIS Model (Rev. A)

SLVMCP2A.ZIP (68 KB) - IBIS 모델
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패키지 핀 CAD 기호, 풋프린트 및 3D 모델
FCBGA (ACF) 256 Ultra Librarian
FCBGA (ALJ) 256 Ultra Librarian
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