제품 상세 정보

Number of outputs 8 Core supply voltage (V) 5 Output supply voltage (V) 5 Output skew (ps) 0.75 Operating temperature range (°C) -40 to 85 Rating Catalog Output type CMOS Input type TTL
Number of outputs 8 Core supply voltage (V) 5 Output supply voltage (V) 5 Output skew (ps) 0.75 Operating temperature range (°C) -40 to 85 Rating Catalog Output type CMOS Input type TTL
SOIC (DW) 20 131.84 mm² (12.8 mm × 10.3 mm)
  • Low Output Skew, Low Pulse Skew for Clock-Distribution and Clock-Generation Applications
  • TTL-Compatible Inputs and CMOS-Compatible Outputs
  • Distributes One Clock Input to Eight Outputs
    • Four Same-Frequency Outputs
    • Four Half-Frequency Outputs
  • Distributed VCC and Ground Pins Reduce Switching Noise
  • High-Drive Outputs (-48-mA IOH, 48-mA IOL)
  • State-of-the-Art EPIC-II BTM BiCMOS Design Significantly Reduces Power Dissipation
  • Package Options Include Plastic Small-Outline (DW)

    EPIC-IIB is a trademark of Texas Instruments Incorporated.

  • Low Output Skew, Low Pulse Skew for Clock-Distribution and Clock-Generation Applications
  • TTL-Compatible Inputs and CMOS-Compatible Outputs
  • Distributes One Clock Input to Eight Outputs
    • Four Same-Frequency Outputs
    • Four Half-Frequency Outputs
  • Distributed VCC and Ground Pins Reduce Switching Noise
  • High-Drive Outputs (-48-mA IOH, 48-mA IOL)
  • State-of-the-Art EPIC-II BTM BiCMOS Design Significantly Reduces Power Dissipation
  • Package Options Include Plastic Small-Outline (DW)

    EPIC-IIB is a trademark of Texas Instruments Incorporated.

The CDC337 is a high-performance, low-skew clock driver. It is specifically designed for applications requiring synchronized output signals at both the clock frequency and one-half the clock frequency. The four Y outputs switch in phase and at the same frequency as the clock (CLK) input. The four Q outputs switch at one-half the frequency of CLK.

When the output-enable (OE\) input is low and the clear (CLR\) input is high, the Y outputs follow CLK and the Q outputs toggle on low-to-high transitions at CLK. Taking CLR\ low asynchronously resets the Q outputs to the low level. When OE\ is high, the outputs are in the high-impedance state.

The CDC337 is characterized for operation from -40°C to 85°C.

The CDC337 is a high-performance, low-skew clock driver. It is specifically designed for applications requiring synchronized output signals at both the clock frequency and one-half the clock frequency. The four Y outputs switch in phase and at the same frequency as the clock (CLK) input. The four Q outputs switch at one-half the frequency of CLK.

When the output-enable (OE\) input is low and the clear (CLR\) input is high, the Y outputs follow CLK and the Q outputs toggle on low-to-high transitions at CLK. Taking CLR\ low asynchronously resets the Q outputs to the low level. When OE\ is high, the outputs are in the high-impedance state.

The CDC337 is characterized for operation from -40°C to 85°C.

다운로드 스크립트와 함께 비디오 보기 비디오

기술 자료

검색된 결과가 없습니다. 검색어를 지우고 다시 시도하세요.
1개 모두 보기
상위 문서 유형 직함 형식 옵션 최신 영어 버전 다운로드 날짜
* 데이터 시트 Clock Driver With 3-State Outputs datasheet (Rev. B) 1998. 10. 27

설계 및 개발

추가 조건 또는 필수 리소스는 사용 가능한 경우 아래 제목을 클릭하여 세부 정보 페이지를 확인하세요.

패키지 CAD 기호, 풋프린트 및 3D 모델
SOIC (DW) 20 Ultra Librarian

주문 및 품질

권장 제품에는 본 TI 제품과 관련된 매개 변수, 평가 모듈 또는 레퍼런스 디자인이 있을 수 있습니다.

지원 및 교육

TI 엔지니어의 기술 지원을 받을 수 있는 TI E2E™ 포럼

콘텐츠는 TI 및 커뮤니티 기고자에 의해 "있는 그대로" 제공되며 TI의 사양으로 간주되지 않습니다. 사용 약관을 참조하십시오.

품질, 패키징, TI에서 주문하는 데 대한 질문이 있다면 TI 지원을 방문하세요. ​​​​​​​​​​​​​​

동영상