제품 상세 정보

Number of outputs 9 Output type LVCMOS Output frequency (max) (MHz) 230 Core supply voltage (V) 1.8 Output supply voltage (V) 1.8 Input type XTAL Operating temperature range (°C) -40 to 85 Features Integrated EEPROM, Multiplier or divider, Spread-spectrum clocking (SSC) Rating Catalog
Number of outputs 9 Output type LVCMOS Output frequency (max) (MHz) 230 Core supply voltage (V) 1.8 Output supply voltage (V) 1.8 Input type XTAL Operating temperature range (°C) -40 to 85 Features Integrated EEPROM, Multiplier or divider, Spread-spectrum clocking (SSC) Rating Catalog
TSSOP (PW) 24 49.92 mm² (7.8 mm × 6.4 mm)
  • Member of programmable clock generator family
    • CDCEx913: 1 PLL, 3 outputs
    • CDCEx925: 2 PLLs, 5 outputs
    • CDCEx937: 3 PLLs, 7 outputs
    • CDCEx949: 4 PLLs, 9 outputs
  • In-system programmability and EEPROM
    • Serial programmable volatile register
    • Nonvolatile EEPROM to store customer settings
  • Flexible input clocking concept
    • External crystal: 8MHz to 32MHz
    • On-chip VCXO pull-range: ±150ppm
    • Single-ended LVCMOS up to 160MHz
  • Free selectable output frequency up to 230MHz
  • Low-noise PLL core
    • PLL loop filter components integrated
    • Low period jitter: 60ps (typical)
  • Separate output supply pins
    • CDCE949: 3.3V and 2.5V
    • CDCEL949: 1.8V
  • Flexible clock driver
    • Three user-definable control inputs [S0/S1/S2] (for example: SSC selection, frequency switching, output enable or power down)
    • Generates highly accurate clocks for video, audio, USB, IEEE1394, RFID, Bluetooth, WLAN, Ethernet™, and GPS
    • Generates common clock frequencies used with TI-DaVinci™, OMAP™, DSPs
    • Programmable SSC modulation
    • Enables 0ppm clock generation
  • 1.8V device core supply
  • Wide temperature range: –40°C to 85°C
  • Packaged in TSSOP
  • Development and programming kit for easy PLL design and programming (TI Pro-Clock™)
  • Member of programmable clock generator family
    • CDCEx913: 1 PLL, 3 outputs
    • CDCEx925: 2 PLLs, 5 outputs
    • CDCEx937: 3 PLLs, 7 outputs
    • CDCEx949: 4 PLLs, 9 outputs
  • In-system programmability and EEPROM
    • Serial programmable volatile register
    • Nonvolatile EEPROM to store customer settings
  • Flexible input clocking concept
    • External crystal: 8MHz to 32MHz
    • On-chip VCXO pull-range: ±150ppm
    • Single-ended LVCMOS up to 160MHz
  • Free selectable output frequency up to 230MHz
  • Low-noise PLL core
    • PLL loop filter components integrated
    • Low period jitter: 60ps (typical)
  • Separate output supply pins
    • CDCE949: 3.3V and 2.5V
    • CDCEL949: 1.8V
  • Flexible clock driver
    • Three user-definable control inputs [S0/S1/S2] (for example: SSC selection, frequency switching, output enable or power down)
    • Generates highly accurate clocks for video, audio, USB, IEEE1394, RFID, Bluetooth, WLAN, Ethernet™, and GPS
    • Generates common clock frequencies used with TI-DaVinci™, OMAP™, DSPs
    • Programmable SSC modulation
    • Enables 0ppm clock generation
  • 1.8V device core supply
  • Wide temperature range: –40°C to 85°C
  • Packaged in TSSOP
  • Development and programming kit for easy PLL design and programming (TI Pro-Clock™)

The CDCE949 and CDCEL949 are modular PLL-based low cost, high-performance, programmable clock synthesizers, multipliers, and dividers. These devices generate up to nine output clocks from a single input frequency. Each output is programmable in-system for any clock frequency up to 230MHz, using up to four independent configurable PLLs.

The CDCEx949 has separate output supply pins (VDDOUT): 1.8V for the CDCEL949 and 2.5V to 3.3V for the CDCE949.

The input accepts an external crystal or LVCMOS clock signal. If an external crystal is used, an on-chip load capacitor is adequate for most applications. The value of the load capacitor is programmable from 0pF to 20pF. Additionally, an on-chip VCXO is selectable, allowing synchronization of the output frequency to an external control signal, that is, a PWM signal.

The deep M/N divider ratio allows the generation of 0ppm audio or video, networking (WLAN, Bluetooth, Ethernet, GPS) or Interface (USB, IEEE1394, Memory Stick) clocks from a reference input frequency, such as 27MHz.

All PLLs support spread spectrum clocking (SSC). SSC can be center-spread or down-spread clocking. This is a common technique to reduce electromagnetic interference (EMI).

Based on the PLL frequency and the divider settings, the internal loop-filter components are automatically adjusted to achieve high stability, and to optimize the jitter-transfer characteristics of each PLL.

The device supports non-volatile EEPROM programming for easy customization of the device to the application. The CDCEx949 is preset to a factory-default configuration. The device can be reprogrammed to a different application configuration before PCB assembly, or reprogrammed by in-system programming. All device settings are programmable through the SDA and SCL bus, a 2-wire serial interface.

The CDCE949 and CDCEL949 are modular PLL-based low cost, high-performance, programmable clock synthesizers, multipliers, and dividers. These devices generate up to nine output clocks from a single input frequency. Each output is programmable in-system for any clock frequency up to 230MHz, using up to four independent configurable PLLs.

The CDCEx949 has separate output supply pins (VDDOUT): 1.8V for the CDCEL949 and 2.5V to 3.3V for the CDCE949.

The input accepts an external crystal or LVCMOS clock signal. If an external crystal is used, an on-chip load capacitor is adequate for most applications. The value of the load capacitor is programmable from 0pF to 20pF. Additionally, an on-chip VCXO is selectable, allowing synchronization of the output frequency to an external control signal, that is, a PWM signal.

The deep M/N divider ratio allows the generation of 0ppm audio or video, networking (WLAN, Bluetooth, Ethernet, GPS) or Interface (USB, IEEE1394, Memory Stick) clocks from a reference input frequency, such as 27MHz.

All PLLs support spread spectrum clocking (SSC). SSC can be center-spread or down-spread clocking. This is a common technique to reduce electromagnetic interference (EMI).

Based on the PLL frequency and the divider settings, the internal loop-filter components are automatically adjusted to achieve high stability, and to optimize the jitter-transfer characteristics of each PLL.

The device supports non-volatile EEPROM programming for easy customization of the device to the application. The CDCEx949 is preset to a factory-default configuration. The device can be reprogrammed to a different application configuration before PCB assembly, or reprogrammed by in-system programming. All device settings are programmable through the SDA and SCL bus, a 2-wire serial interface.

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기술 자료

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8개 모두 보기
상위 문서 유형 직함 형식 옵션 최신 영어 버전 다운로드 날짜
* 데이터 시트 CDCE(L)949: Flexible Low Power LVCMOS Clock Generator With SSC Support for EMI Reduction datasheet (Rev. H) PDF | HTML 2025. 7. 23
애플리케이션 노트 VCXO Application Guideline for CDCE(L)9xx Family (Rev. A) 2012. 4. 23
사용 설명서 CDCE(L)9XX & CDCEx06 Programming Evaluation Module Manual (Rev. A) 2010. 11. 22
사용 설명서 CDCE(L)9xx Performance Evaluation Module (Rev. A) 2010. 7. 7
애플리케이션 노트 Troubleshooting I2C Bus Protocol 2009. 10. 19
애플리케이션 노트 Usage of I2C for CDCE(L)949, CDCE(L)937, CDCE(L)925, CDCE(L)913 2009. 9. 23
애플리케이션 노트 Generating Low Phase-Noise Clocks for Audio Data Converters from Low Frequency 2008. 3. 31
애플리케이션 노트 Practical consideration on choosing a crystal for CDCE(L)9xx family 2008. 3. 24

설계 및 개발

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평가 보드

CDCEL949PERF-EVM — CDCEL949 성능 평가 모듈

The CDCEL949PERF-EVM will help to verify the functionality and performance of CDCEL949 with the options of crystal and 1.8 V LVCMOS inputs. The outputs can be connected to the Oscilloscope directly with SMA cables. The below information/items are included: The EVM use's guide : SCAU022; the (...)

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평가 보드

CDCEL9XXPROGEVM — CDCE(L)949 제품군 EEPROM 프로그래밍 보드

The clock generator CDCE(L)949 family has integrated EEPROM that allows the default frequency settings to be saved upon start up. CDCEL9XXPROGEVM is a programming board that allows a fast programming of prototyping samples or small production quantities. It applies to all 8 devices in the family: (...)

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드라이버 또는 라이브러리

SCAC131 — Drivers for the CDCEL9xx programmer EVM

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지원 소프트웨어

CLOCKPRO — ClockPro Software

TI's ClockPro software allows users to program/configure the following devices in a friendly GUI interface:

  • CDCE949
  • CDCE937
  • CDCE925
  • CDCE913
  • CDCE906
  • CDCE706
  • CDCEL949
  • CDCEL937
  • CDCEL925
  • CDCEL913

It is intended to be used with the evaluation modules of the above devices.

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지원 소프트웨어

SCAC073 — TI-Pro-Clock Programming Software

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설계 툴

CLOCK-TREE-ARCHITECT — 클록 트리 아키텍트 프로그래밍 소프트웨어

클록 트리 아키텍트는 시스템 요구 사항에 따라 클록 트리 솔루션을 생성하여 설계 프로세스를 간소화하는 클록 트리 합성 툴입니다. 이 툴은 광범위한 클로킹 제품 데이터베이스에서 데이터를 가져와 시스템 수준의 다중 칩 클로킹 솔루션을 생성합니다.

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패키지 CAD 기호, 풋프린트 및 3D 모델
TSSOP (PW) 24 Ultra Librarian

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