ISO5852S-EP
- 100-kV/μs Minimum Common-Mode Transient Immunity (CMTI) at VCM = 1500 V
- Split Outputs to Provide 2.5-A Peak Source and 5-A Peak Sink Currents
- Short Propagation Delay: 76 ns (Typ), 110 ns (Max)
- 2-A Active Miller Clamp
- Output Short-Circuit Clamp
- Soft Turn-Off (STO) during Short Circuit
- Fault Alarm upon Desaturation Detection is Signaled on FLT and Reset Through RST
- Input and Output Undervoltage Lockout (UVLO) with Ready (RDY) Pin Indication
- Active Output Pulldown and Default Low Outputs with Low Supply or Floating Inputs
- 2.25-V to 5.5-V Input Supply Voltage
- 15-V to 30-V Output Driver Supply Voltage
- CMOS Compatible Inputs
- Rejects Input Pulses and Noise Transients Shorter Than 20 ns
- Operating Temperature: –55°C to +125°C Ambient
- Surge Immunity 12800-VPK (according to IEC 61000-4-5)
- Safety-Related Certifications:
- 8000-VPK VIOTM and 2121-VPK VIORM Reinforced Isolation per DIN V VDE V 0884-10 (VDE V 0884-10):2006-12
- 5700-VRMS Isolation for 1 Minute per UL 1577
- CSA Component Acceptance Notice 5A, IEC 60950-1, IEC 60601-1 and IEC 61010-1 End Equipment Standards
- CQC Certification per GB4943.1-2011
- All Certifications Complete per UL, VDE, CQC, TUV and Planned for CSA
The ISO5852S-EP device is a 5.7-kVRMS, reinforced isolated gate driver for IGBTs and MOSFETs with split outputs, OUTH and OUTL, providing 2.5-A source and 5-A sink current. The input side operates from a single 2.25-V to 5.5-V supply. The output side allows for a supply range from minimum 15-V to maximum 30-V. Two complementary CMOS inputs control the output state of the gate driver. The short propagation time of 76 ns provides accurate control of the output stage.
An internal desaturation (DESAT) fault detection recognizes when the IGBT is in an overcurrent condition. Upon a DESAT detect, a mute logic immediately blocks the output of the isolator and initiates a soft-turnoff procedure which disables the OUTH pin and pulls the OUTL pin to low over a time span of 2 µs. When the OUTL pin reaches 2 V with respect to the most-negative supply potential, VEE2, the gate-driver output is pulled hard to the VEE2 potential which turns the IGBT immediately off.
When desaturation is active, a fault signal is sent across the isolation barrier pulling the FLT output at the input side low and blocking the isolator input. Mute logic is activated through the soft-turnoff period. The FLT output condition is latched and can be reset only after the RDY pin goes high, through a low-active pulse at the RST input.
When the IGBT is turned off during normal operation with a bipolar output supply, the output is hard clamp to VEE2. If the output supply is unipolar, an active Miller clamp can be used, allowing Miller current to sink across a low-impedance path which prevents the IGBT from dynamic turnon during high-voltage transient conditions.
The readiness for the gate driver to be operated is under the control of two undervoltage-lockout circuits monitoring the input-side and output-side supplies. If either side has insufficient supply, the RDY output goes low, otherwise this output is high.
The ISO5852S-EP device is available in a 16-pin SOIC package. Device operation is specified over a temperature range from –55°C to +125°C ambient.
기술 문서
| 유형 | 직함 | 날짜 | ||
|---|---|---|---|---|
| * | Data sheet | ISO5852S-EP High-CMTI 2.5-A and 5-A Reinforced Isolated IGBT, MOSFET Gate Driver With Split Outputs and Active Protection Features datasheet | PDF | HTML | 2016/12/23 |
| * | Radiation & reliability report | ISO5852SMDWREP Reliability Report | 2017/04/20 | |
| User guide | UCC217xx and ISO5x5x Half-Bridge EVM User's Guide for Wolfspeed 1200-V SiC | 2023/09/01 | ||
| Application note | Comparative Analysis of Two Different Methods for Gate-Drive Current Boosting (Rev. A) | PDF | HTML | 2022/02/17 | |
| Application brief | External Gate Resistor Selection Guide (Rev. A) | 2020/02/28 | ||
| Application brief | Understanding Peak IOH and IOL Currents (Rev. A) | 2020/02/28 |
설계 및 개발
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ISO5852SEVM — 강화 절연 IGBT 게이트 드라이버 평가 모듈
This evaluation module, featuring ISO5852S reinforced isolated gate driver device, allows designers to evaluate device AC and DC performance with a pre-populated 1-nF load or with a user-installed IGBT in either of the standard TO-247 or TO-220 packages.
PSPICE-FOR-TI — TI 설계 및 시뮬레이션 툴용 PSpice®
TI 설계 및 시뮬레이션 환경용 PSpice는 기본 제공 라이브러리를 이용해 복잡한 혼합 신호 설계를 시뮬레이션할 수 있습니다. 레이아웃 및 제작에 (...)
| 패키지 | 핀 | 다운로드 |
|---|---|---|
| SOIC (DW) | 16 | 옵션 보기 |
주문 및 품질
- RoHS
- REACH
- 디바이스 마킹
- 납 마감/볼 재질
- MSL 등급/피크 리플로우
- MTBF/FIT 예측
- 물질 성분
- 인증 요약
- 지속적인 신뢰성 모니터링
- 팹 위치
- 조립 위치
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