LMK04616

활성

초저잡음 및 저전력 JESD204B 호환 클럭 지터 클리너

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document-pdfAcrobat LMK04616 Ultra-Low Noise and Low Power JESD204B Compliant Clock Jitter Cleaner With Dual-Loop PLLs datasheet (Rev. B) (영어) PDF | HTML

LMK04616

활성

데이터 시트

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제품 상세 정보

Number of input channels

4

Number of outputs

16

RMS jitter (fs)

65

Features

JESD204B

Output frequency (min) (MHz)

0.03

Output frequency (max) (MHz)

2000

Output type

LVDS, LVPECL

Input type

LVCMOS, LVDS, LVPECL

Operating temperature range (°C)

-40 to 85

Number of input channels

4

Number of outputs

16

RMS jitter (fs)

65

Features

JESD204B

Output frequency (min) (MHz)

0.03

Output frequency (max) (MHz)

2000

Output type

LVDS, LVPECL

Input type

LVCMOS, LVDS, LVPECL

Operating temperature range (°C)

-40 to 85

NFBGA (ZCR)

144

100 mm² (10 mm × 10 mm)

Dual-loop PLL architecture
Ultra low noise (10 kHz to 20 MHz):
- 48-fs RMS jitter at 1966.08 MHz
- 50-fs RMS jitter at 983.04 MHz
- 61-fs RMS jitter at 122.88 MHz
–165-dBc/Hz noise floor at 122.88 MHz
JESD204B support
- Single shot, pulsed, and continuous SYSREF
16 differential output clocks in 8 frequency groups
- Programmable output swing between 700 mVpp to 1600 mVpp
- Each output pair can be configured to SYSREF clock output
- 16-bit channel divider
- Minimum SYSREF frequency of 25 kHz
- Maximum output frequency of 2 GHz
- Precision digital delay, dynamically adjustable
  - Digital delay (DDLY) of ½ × clock distribution path frequency (2 GHz maximum)
- 60-ps step analog delay
- 50% duty cycle output divides, 1 to 65535
  (even and odd)
Four reference inputs
- Holdover mode, when inputs are lost
- Automatic and manual switch-over modes
- Loss-of-signal (LOS) detection
1.05-W typical power consumption with 16 outputs active
Operates typically from a 1.8-V (outputs, inputs) and 3.3-V supply (digital, PLL1, PLL2_OSC, PLL2 core)
Fully integrated programmable loop filter
PLL2
- PLL2 phase detector rate up to 250 MHz
- OSCin frequency-doubler
- Integrated low-noise VCO
Internal power conditioning: better than –80 dBc PSRR on VDDO for 122.88-MHz differential outputs
3- or 4-wire SPI interface (4-wire is default)
–40ºC to +85ºC industrial ambient temperature
Supports 105ºC PCB temperature (measured at thermal pad)
LMK04616: 10-mm × 10-mm NFBGA-144 package with 0.8-mm pitch

Dual-loop PLL architecture
Ultra low noise (10 kHz to 20 MHz):
- 48-fs RMS jitter at 1966.08 MHz
- 50-fs RMS jitter at 983.04 MHz
- 61-fs RMS jitter at 122.88 MHz
–165-dBc/Hz noise floor at 122.88 MHz
JESD204B support
- Single shot, pulsed, and continuous SYSREF
16 differential output clocks in 8 frequency groups
- Programmable output swing between 700 mVpp to 1600 mVpp
- Each output pair can be configured to SYSREF clock output
- 16-bit channel divider
- Minimum SYSREF frequency of 25 kHz
- Maximum output frequency of 2 GHz
- Precision digital delay, dynamically adjustable
  - Digital delay (DDLY) of ½ × clock distribution path frequency (2 GHz maximum)
- 60-ps step analog delay
- 50% duty cycle output divides, 1 to 65535
  (even and odd)
Four reference inputs
- Holdover mode, when inputs are lost
- Automatic and manual switch-over modes
- Loss-of-signal (LOS) detection
1.05-W typical power consumption with 16 outputs active
Operates typically from a 1.8-V (outputs, inputs) and 3.3-V supply (digital, PLL1, PLL2_OSC, PLL2 core)
Fully integrated programmable loop filter
PLL2
- PLL2 phase detector rate up to 250 MHz
- OSCin frequency-doubler
- Integrated low-noise VCO
Internal power conditioning: better than –80 dBc PSRR on VDDO for 122.88-MHz differential outputs
3- or 4-wire SPI interface (4-wire is default)
–40ºC to +85ºC industrial ambient temperature
Supports 105ºC PCB temperature (measured at thermal pad)
LMK04616: 10-mm × 10-mm NFBGA-144 package with 0.8-mm pitch

The LMK0461x device family is the industry’s highest performance and lowest power jitter cleaner with JESD204B support. The 16 clock outputs can be configured to drive eight JESD204B converters or other logic devices using device and SYSREF clocks. The 17th output can be configured to provide a signal from PLL2 or a copy from the external VCXO.

Features like fully integrated PLL1 and PLL2 loop filters, a high number of integrated LDOs, digital and analog delay, the flexibility to supply outputs with 3.3V, 2.5V and 1.8V as well as the option to generate multiple SYSREF domains simultaneously makes the device easy to use.

Not limited to JESD204B applications each of the 17 outputs can be configured for traditional clocking systems.

The LMK0461x device family is the industry’s highest performance and lowest power jitter cleaner with JESD204B support. The 16 clock outputs can be configured to drive eight JESD204B converters or other logic devices using device and SYSREF clocks. The 17th output can be configured to provide a signal from PLL2 or a copy from the external VCXO.

Features like fully integrated PLL1 and PLL2 loop filters, a high number of integrated LDOs, digital and analog delay, the flexibility to supply outputs with 3.3V, 2.5V and 1.8V as well as the option to generate multiple SYSREF domains simultaneously makes the device easy to use.

Not limited to JESD204B applications each of the 17 outputs can be configured for traditional clocking systems.

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기술 자료

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4개 모두 보기

상위 문서	유형	직함	형식 옵션	날짜
*	데이터 시트	LMK04616 Ultra-Low Noise and Low Power JESD204B Compliant Clock Jitter Cleaner With Dual-Loop PLLs datasheet (Rev. B)	PDF \| HTML	2018. 1. 9
	애플리케이션 노트	JESD204B Multi-Device Synchronization Using LMK0461x	PDF \| HTML	2017. 8. 16
	애플리케이션 노트	LMK0461x Phase Noise Performance With DC-DC Converters (Rev. B)		2017. 7. 20
	애플리케이션 노트	SDPLL for LMK046xx Family		2017. 5. 15

설계 및 개발

추가 조건 또는 필수 리소스는 사용 가능한 경우 아래 제목을 클릭하여 세부 정보 페이지를 확인하세요.

평가 보드

LMK04616EVM — LMK04616 평가 모듈

LMK04616EVM은 LMK04616 초저잡음 및 저전력 JESD204B 호환 듀얼 루프 지터 클리너를 사용합니다. 16개 출력을 실행하는 1200mW의 소비 전력을 지원하는 LMK04616은 저잡음 VCXO 모듈을 사용하여 65 fs 지터(12kHz~20MHz)를 지원합니다. 통합 LDO는 DC/DC 컨버터의 사용을 지원하는 높은 PSRR을 제공합니다.

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지원 소프트웨어

TICSPRO-SW — TICS Pro GUI and Live Programming Tool for Clocking Devices

텍사스 인스트루먼트 클록 및 신시사이저(TICS) Pro 소프트웨어는 다음 접두사를 사용하여 제품 번호의 평가 모듈(EVM)을 프로그래밍하는 데 사용됩니다. CDC, LMK 및 LMX. 이러한 제품에는 위상 동기 루프 및 전압 제어 오실레이터(PLL+VCO), 신시사이저 및 클로킹 디바이스가 포함되어 있습니다.

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