LMK1D1216

활성

16채널 출력 LVDS 1.8V, 2.5V 및 3.3V LVDS 버퍼

지금 주문하기

데이터 시트

document-pdfAcrobat LMK1D121x Low Additive Jitter LVDS Buffer datasheet (Rev. A) (영어) PDF | HTML

LMK1D1216

활성

데이터 시트

지금 주문하기

제품 상세 정보

Number of outputs

16

Additive RMS jitter (typ) (fs)

45

Core supply voltage (V)

1.8, 2.5, 3.3

Output supply voltage (V)

1.8, 2.5, 3.3

Output skew (ps)

20

Operating temperature range (°C)

-40 to 105

Rating

Catalog

Output type

LVDS

Input type

HCSL, LP-HCSL, LVCMOS, LVDS, LVPECL

Number of outputs

16

Additive RMS jitter (typ) (fs)

45

Core supply voltage (V)

1.8, 2.5, 3.3

Output supply voltage (V)

1.8, 2.5, 3.3

Output skew (ps)

20

Operating temperature range (°C)

-40 to 105

Rating

Catalog

Output type

LVDS

Input type

HCSL, LP-HCSL, LVCMOS, LVDS, LVPECL

VQFN (RGZ)

48

49 mm² (7 mm × 7 mm)

High-performance LVDS clock buffer family: up to 2 GHz
- 2:12 differential buffer (LMK1D1212)
- 2:16 differential buffer (LMK1D1216)
Supply voltage: 1.71 V to 3.465 V
Low additive jitter: < 60 fs RMS maximum in 12-kHz to 20-MHz at 156.25 MHz
- Very low phase noise floor: -164 dBc/Hz (typical)
Very low propagation delay: < 575 ps maximum
Output skew: 20 ps maximum
High-swing LVDS (boosted mode): 500-mV VOD typical when AMP_SEL = 1
Universal inputs accept LVDS, LVPECL, LVCMOS, HCSL and CML signal levels
LVDS reference voltage, V AC_REF, available for capacitive-coupled inputs
Industrial temperature range: –40°C to 105°C
Packaged in
- LMK1D1212: 6-mm × 6-mm, 40-pin VQFN (RHA)
- LMK1D1216: 7-mm × 7-mm, 48-pin VQFN (RGZ)

High-performance LVDS clock buffer family: up to 2 GHz
- 2:12 differential buffer (LMK1D1212)
- 2:16 differential buffer (LMK1D1216)
Supply voltage: 1.71 V to 3.465 V
Low additive jitter: < 60 fs RMS maximum in 12-kHz to 20-MHz at 156.25 MHz
- Very low phase noise floor: -164 dBc/Hz (typical)
Very low propagation delay: < 575 ps maximum
Output skew: 20 ps maximum
High-swing LVDS (boosted mode): 500-mV VOD typical when AMP_SEL = 1
Universal inputs accept LVDS, LVPECL, LVCMOS, HCSL and CML signal levels
LVDS reference voltage, V AC_REF, available for capacitive-coupled inputs
Industrial temperature range: –40°C to 105°C
Packaged in
- LMK1D1212: 6-mm × 6-mm, 40-pin VQFN (RHA)
- LMK1D1216: 7-mm × 7-mm, 48-pin VQFN (RGZ)

The LMK1D1212 clock buffer distributes with minimum skew one of two selectable clock inputs (IN0, IN1) to 12 pairs of differential LVDS clock outputs (OUT0 through OUT11). Similarly, the LMK1D1216 distributes 16 pairs of differential LVDS clock outputs (OUT0 through OUT15). The LMK1D121x family can accept two clock sources into an input multiplexer. The inputs can either be LVDS, LVPECL, LP-HCSL, HCSL, CML, or LVCMOS.

The LMK1D121x is specifically designed for driving 50-Ω transmission lines. When driving inputs in single-ended mode, apply the appropriate bias voltage to the unused negative input pin.

The IN_SEL pin selects the input which is routed to the outputs. If this pin is left open, it disables the outputs (static low). The part supports a fail-safe function. The device further incorporates an input hysteresis which prevents random oscillation of the outputs in the absence of an input signal.

The device operates in 1.8-V or 2.5-V or 3.3-V supply environment and is characterized from –40°C to 105°C (ambient temperature).

The LMK1D1212 clock buffer distributes with minimum skew one of two selectable clock inputs (IN0, IN1) to 12 pairs of differential LVDS clock outputs (OUT0 through OUT11). Similarly, the LMK1D1216 distributes 16 pairs of differential LVDS clock outputs (OUT0 through OUT15). The LMK1D121x family can accept two clock sources into an input multiplexer. The inputs can either be LVDS, LVPECL, LP-HCSL, HCSL, CML, or LVCMOS.

The LMK1D121x is specifically designed for driving 50-Ω transmission lines. When driving inputs in single-ended mode, apply the appropriate bias voltage to the unused negative input pin.

The IN_SEL pin selects the input which is routed to the outputs. If this pin is left open, it disables the outputs (static low). The part supports a fail-safe function. The device further incorporates an input hysteresis which prevents random oscillation of the outputs in the absence of an input signal.

The device operates in 1.8-V or 2.5-V or 3.3-V supply environment and is characterized from –40°C to 105°C (ambient temperature).

filter

기타 클록 버퍼 찾기

다운로드 스크립트와 함께 비디오 보기 비디오

관심 가지실만한 유사 제품

open-in-new

대안 비교

비교 대상 장치와 유사한 기능.

LMK1D2108

활성

듀얼 뱅크 8채널 출력 1.8V, 2.5V 및 3.3V LVDS 버퍼 Same performance with dual 1:8 rather than MUXed 1:16

기술 자료

검색된 결과가 없습니다. 검색어를 지우고 다시 시도하세요.

2개 모두 보기

상위 문서	유형	직함	형식 옵션	최신 영어 버전 다운로드	날짜
*	데이터 시트	LMK1D121x Low Additive Jitter LVDS Buffer datasheet (Rev. A)	PDF \| HTML		2023. 4. 12
	인증서	LMK1D1216EVM EU RoHS Declaration of Conformity (DoC)			2021. 8. 19

설계 및 개발

추가 조건 또는 필수 리소스는 사용 가능한 경우 아래 제목을 클릭하여 세부 정보 페이지를 확인하세요.

평가 보드

LMK1D1216EVM — LMK1D1216 저지터 2:16 LVDS 팬 아웃 버퍼 평가 모듈

LMK1D1216은 고성능 저 가산 지터 LVDS 클록 버퍼로, 차동 입력 2개와 LVDS 출력이 16개 있습니다. 이 평가 모듈(EVM)은 LMK1D1216의 전기 성능을 시연할 수 있도록 설계했습니다. 그러나 이 EVM은 LMK1Dxxxx 제품군의 다른 48핀 디바이스 평가에도 사용할 수 있습니다. LMK1D1216EVM에는 최고의 성능을 위해 50Ω SMA 커넥터와 임피던스 제어 50Ω 마이크로스트립 전송선이 내장되어 있습니다.

사용 설명서: PDF | HTML

지원되는 제품 및 하드웨어

재고 있음

제한:

주문하려면 로그인

lock

재고를 보려면 로그인

??asset.out-of-stock-ti_ko_KR??

이용할 수 없음

시뮬레이션 모델