LMK1D2106

활성

듀얼 뱅크 6채널 출력 1.8V, 2.5V 및 3.3V LVDS 버퍼

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document-pdfAcrobat LMK1D210x Low Additive Jitter LVDS Buffer datasheet (Rev. A) (영어) PDF | HTML

LMK1D2106

활성

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제품 상세 정보

Number of outputs

12

Additive RMS jitter (typ) (fs)

45

Core supply voltage (V)

1.8, 2.5, 3.3

Output supply voltage (V)

1.8, 2.5, 3.3

Output skew (ps)

20

Operating temperature range (°C)

-40 to 105

Rating

Catalog

Output type

LVDS

Input type

HCSL, LP-HCSL, LVCMOS, LVDS, LVPECL

Number of outputs

12

Additive RMS jitter (typ) (fs)

45

Core supply voltage (V)

1.8, 2.5, 3.3

Output supply voltage (V)

1.8, 2.5, 3.3

Output skew (ps)

20

Operating temperature range (°C)

-40 to 105

Rating

Catalog

Output type

LVDS

Input type

HCSL, LP-HCSL, LVCMOS, LVDS, LVPECL

VQFN (RHA)

40

36 mm² (6 mm × 6 mm)

High-performance LVDS clock buffer family: up to 2 GHz
- Dual 1:6 differential buffer
- Dual 1:8 differential buffer
Supply voltage: 1.71 V to 3.465 V
Low additive jitter: < 60 fs RMS maximum in 12-kHz to 20-MHz at 156.25 MHz
- Very low phase noise floor: -164 dBc/Hz (typical)
Very low propagation delay: < 575 ps maximum
Output skew: 20 ps maximum
High-swing LVDS (boosted mode): 500-mV VOD typical when AMP_SEL = 1
Bank enable/disable using the EN pin
Fail-safe input operation
Universal inputs accept LVDS, LVPECL, LVCMOS, HCSL and CML signal levels
LVDS reference voltage, V_{AC_REF}, available for capacitive-coupled inputs
Industrial temperature range: –40°C to 105°C
Packaged in
- LMK1D2106: 6-mm × 6-mm, 40-pin VQFN (RHA)
- LMK1D2108: 7-mm × 7-mm, 48-pin VQFN (RGZ)

High-performance LVDS clock buffer family: up to 2 GHz
- Dual 1:6 differential buffer
- Dual 1:8 differential buffer
Supply voltage: 1.71 V to 3.465 V
Low additive jitter: < 60 fs RMS maximum in 12-kHz to 20-MHz at 156.25 MHz
- Very low phase noise floor: -164 dBc/Hz (typical)
Very low propagation delay: < 575 ps maximum
Output skew: 20 ps maximum
High-swing LVDS (boosted mode): 500-mV VOD typical when AMP_SEL = 1
Bank enable/disable using the EN pin
Fail-safe input operation
Universal inputs accept LVDS, LVPECL, LVCMOS, HCSL and CML signal levels
LVDS reference voltage, V_{AC_REF}, available for capacitive-coupled inputs
Industrial temperature range: –40°C to 105°C
Packaged in
- LMK1D2106: 6-mm × 6-mm, 40-pin VQFN (RHA)
- LMK1D2108: 7-mm × 7-mm, 48-pin VQFN (RGZ)

The LMK1D210x clock buffer distributes two clock inputs (IN0 and IN1) to a total of 16 pairs of differential LVDS clock outputs (OUT0 to OUT15) in the LMK1D2108 and 12 pairs of clock outputs (OUT0 to OUT11) in the LMK1D2106 with minimum skew for clock distribution. Each buffer block consists of one input and a maximum of 6 (LMK1D2106) or 8 (LMK1D2108) LVDS outputs. The inputs can either be LVDS, LVPECL, HCSL, CML, or LVCMOS.

The LMK1D210x is specifically designed for driving 50-Ω transmission lines. When driving inputs in single-ended mode, apply the appropriate bias voltage to the unused negative input pin (see Figure 8-6).

Using the control pin (EN), output banks can either be enable or disabled. If this pin is left open, both bank outputs are enabled. If the control pin is switched to a logic "0", both bank outputs are disabled (static logic "0"). If the control pin is switched to a logic "1", the outputs of one bank are disabled while the outputs of the other bank are enabled. The part also supports a fail-safe function. The device further incorporates an input hysteresis which prevents random oscillation of the outputs in the absence of an input signal.

The device operates in a 1.8-V, 2.5-V, or 3.3-V supply environment and is characterized from –40°C to 105°C (ambient temperature).

The LMK1D210x clock buffer distributes two clock inputs (IN0 and IN1) to a total of 16 pairs of differential LVDS clock outputs (OUT0 to OUT15) in the LMK1D2108 and 12 pairs of clock outputs (OUT0 to OUT11) in the LMK1D2106 with minimum skew for clock distribution. Each buffer block consists of one input and a maximum of 6 (LMK1D2106) or 8 (LMK1D2108) LVDS outputs. The inputs can either be LVDS, LVPECL, HCSL, CML, or LVCMOS.

The LMK1D210x is specifically designed for driving 50-Ω transmission lines. When driving inputs in single-ended mode, apply the appropriate bias voltage to the unused negative input pin (see Figure 8-6).

Using the control pin (EN), output banks can either be enable or disabled. If this pin is left open, both bank outputs are enabled. If the control pin is switched to a logic "0", both bank outputs are disabled (static logic "0"). If the control pin is switched to a logic "1", the outputs of one bank are disabled while the outputs of the other bank are enabled. The part also supports a fail-safe function. The device further incorporates an input hysteresis which prevents random oscillation of the outputs in the absence of an input signal.

The device operates in a 1.8-V, 2.5-V, or 3.3-V supply environment and is characterized from –40°C to 105°C (ambient temperature).

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기타 클록 버퍼 찾기

다운로드 스크립트와 함께 비디오 보기 비디오

관심 가지실만한 유사 제품

open-in-new

대안 비교

비교 대상 장치와 유사한 기능.

LMK1D1212

활성

12채널 출력 LVDS 1.8V, 2.5V 및 3.3V LVDS 버퍼 Same performance with MUXed 1:12

기술 자료

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1개 모두 보기

상위 문서	유형	직함	형식 옵션	최신 영어 버전 다운로드		날짜
*	데이터 시트	LMK1D210x Low Additive Jitter LVDS Buffer datasheet (Rev. A)	PDF \| HTML		2022. 1. 28

설계 및 개발

추가 조건 또는 필수 리소스는 사용 가능한 경우 아래 제목을 클릭하여 세부 정보 페이지를 확인하세요.

평가 보드

LMK1D1212EVM — LMK1D1212 저지터 2:12 LVCMOS 팬 아웃 버퍼 평가 모듈

LMK1D1212은 고성능 저 가산 지터 LVDS 클록 버퍼로, 차동 입력 2개와 LVDS 출력이 12개 있습니다. 이 평가 모듈(EVM)은 LMK1D1212의 전기 성능을 시연할 수 있도록 설계했습니다. 이 EVM은 LMK1Dxxxx 제품군의 다른 40핀 디바이스 평가에도 사용할 수 있습니다. LMK1D1212EVM에는 최고의 성능을 위해 50Ω SMA 커넥터와 임피던스 제어 50Ω 마이크로스트립 전송선이 내장되어 있습니다.

사용 설명서: PDF | HTML

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