LMK1D2106L

활성

0.7V 출력 공통 모드 옵션이 있는 듀얼 뱅크 2채널 출력 LVDS 1.8V, 2.5V 및 3.3V 버퍼

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document-pdfAcrobat LMK1D210xL Ultra Low Additive Jitter LVDS Buffer datasheet (Rev. A) (영어) PDF | HTML

LMK1D2106L

활성

데이터 시트

지금 주문하기

제품 상세 정보

Number of outputs

6

Additive RMS jitter (typ) (fs)

5

Core supply voltage (V)

1.8, 2.5, 3.3

Output supply voltage (V)

1.8, 2.5, 3.3

Output skew (ps)

20

Operating temperature range (°C)

-40 to 105

Rating

Catalog

Output type

LVDS

Input type

Universal input

Number of outputs

6

Additive RMS jitter (typ) (fs)

5

Core supply voltage (V)

1.8, 2.5, 3.3

Output supply voltage (V)

1.8, 2.5, 3.3

Output skew (ps)

20

Operating temperature range (°C)

-40 to 105

Rating

Catalog

Output type

LVDS

Input type

Universal input

VQFN (RHA)

40

36 mm² (6 mm × 6 mm)

High-performance LVDS clock buffer family: up to 2GHz
- Dual 1:2 differential buffer
- Dual 1:4 differential buffer
- Dual 1:6 differential buffer
- Dual 1:8 differential buffer
Supply voltage: 1.71V to 3.465V
Dual output common mode voltage operation:
- Output common mode voltage: 0.7V at 1.8V supply voltage.
- Output common mode voltage: 1.2V at 2.5V/3.3V supply voltage
Low additive jitter:
- < 17fs RMS typical in 12kHz to 20MHz at 1250.25MHz
- < 22fs RMS typical in 12kHz to 20MHz at 625MHz
- < 60fs RMS maximum in 12kHz to 20MHz at 156.25MHz
- Very low phase noise floor: -164dBc/Hz (typical at 156.25MHz)
Very low propagation delay: < 575ps maximum
Output skew:
- 15ps maximum (LMK1D2102, LMK1D2104)
- 20ps maximum (LMK1D2106, LMK1D2106)
Part to Part skew: 150ps
High-swing LVDS (boosted mode): 500mV VOD typical when AMP_SELA, AMP_SELB= Floating
Bank enable/disable using AMP_SELA and AMP_SELB
Fail-safe input operation
Universal inputs accept LVDS, LVPECL, LVCMOS, HCSL and CML signal levels
LVDS reference voltage, VAC_REF, available for capacitive-coupled inputs
Extended industrial temperature range: –40°C to 105°C

High-performance LVDS clock buffer family: up to 2GHz
- Dual 1:2 differential buffer
- Dual 1:4 differential buffer
- Dual 1:6 differential buffer
- Dual 1:8 differential buffer
Supply voltage: 1.71V to 3.465V
Dual output common mode voltage operation:
- Output common mode voltage: 0.7V at 1.8V supply voltage.
- Output common mode voltage: 1.2V at 2.5V/3.3V supply voltage
Low additive jitter:
- < 17fs RMS typical in 12kHz to 20MHz at 1250.25MHz
- < 22fs RMS typical in 12kHz to 20MHz at 625MHz
- < 60fs RMS maximum in 12kHz to 20MHz at 156.25MHz
- Very low phase noise floor: -164dBc/Hz (typical at 156.25MHz)
Very low propagation delay: < 575ps maximum
Output skew:
- 15ps maximum (LMK1D2102, LMK1D2104)
- 20ps maximum (LMK1D2106, LMK1D2106)
Part to Part skew: 150ps
High-swing LVDS (boosted mode): 500mV VOD typical when AMP_SELA, AMP_SELB= Floating
Bank enable/disable using AMP_SELA and AMP_SELB
Fail-safe input operation
Universal inputs accept LVDS, LVPECL, LVCMOS, HCSL and CML signal levels
LVDS reference voltage, VAC_REF, available for capacitive-coupled inputs
Extended industrial temperature range: –40°C to 105°C

The LMK1D210xL is a low noise dual clock buffer which distributes one input to a maximum of 2 (LMK1D2102L), 4 (LMK1D2104L), 6 (LMK1D2106L) or 8 (LMK1D2108L) LVDS outputs. The inputs can either be LVDS, LVPECL, HCSL, CML, or LVCMOS.

The LMK1D210xL is specifically designed for driving 50Ω transmission lines. When driving inputs in single-ended mode, apply the appropriate bias voltage to the unused negative input pin (see Figure 8-8).

LMK1D210xL buffer offers two output common mode operation (0.7V and 1.2V) for different operating supply. The device provides flexibility in design for DC-coupled mode applications.

AMP_SELA / AMP_SELB control pin can be used to select different output amplitude LVDS (350mV) or boosted LVDS (500mV). In addition to amplitude selection, outputs can be disabled using the same pin.

The part also supports Fail-Safe Input function for clock and digital input pins. The device further incorporates an input hysteresis which prevents random oscillation of the outputs in the absence of an input signal.

The LMK1D210xL is a low noise dual clock buffer which distributes one input to a maximum of 2 (LMK1D2102L), 4 (LMK1D2104L), 6 (LMK1D2106L) or 8 (LMK1D2108L) LVDS outputs. The inputs can either be LVDS, LVPECL, HCSL, CML, or LVCMOS.

The LMK1D210xL is specifically designed for driving 50Ω transmission lines. When driving inputs in single-ended mode, apply the appropriate bias voltage to the unused negative input pin (see Figure 8-8).

LMK1D210xL buffer offers two output common mode operation (0.7V and 1.2V) for different operating supply. The device provides flexibility in design for DC-coupled mode applications.

AMP_SELA / AMP_SELB control pin can be used to select different output amplitude LVDS (350mV) or boosted LVDS (500mV). In addition to amplitude selection, outputs can be disabled using the same pin.

The part also supports Fail-Safe Input function for clock and digital input pins. The device further incorporates an input hysteresis which prevents random oscillation of the outputs in the absence of an input signal.

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1개 모두 보기

상위 문서	유형	직함	형식 옵션	최신 영어 버전 다운로드	날짜
*	데이터 시트	LMK1D210xL Ultra Low Additive Jitter LVDS Buffer datasheet (Rev. A)	PDF \| HTML		2024. 11. 11

설계 및 개발

추가 조건 또는 필수 리소스는 사용 가능한 경우 아래 제목을 클릭하여 세부 정보 페이지를 확인하세요.

평가 보드

LMK1D1212EVM — LMK1D1212 저지터 2:12 LVCMOS 팬 아웃 버퍼 평가 모듈

LMK1D1212은 고성능 저 가산 지터 LVDS 클록 버퍼로, 차동 입력 2개와 LVDS 출력이 12개 있습니다. 이 평가 모듈(EVM)은 LMK1D1212의 전기 성능을 시연할 수 있도록 설계했습니다. 이 EVM은 LMK1Dxxxx 제품군의 다른 40핀 디바이스 평가에도 사용할 수 있습니다. LMK1D1212EVM에는 최고의 성능을 위해 50Ω SMA 커넥터와 임피던스 제어 50Ω 마이크로스트립 전송선이 내장되어 있습니다.

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