LMK5C33216

활성

BAW와 무선 통신을 위한 JESD204B를 지원하는 초저 지터 클록 싱크로나이저

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데이터 시트

document-pdfAcrobat LMK5C33216 Ultra-Low Jitter Clock Synchronizer with JESD204B for Wireless Communications with BAW datasheet (Rev. B) (영어) PDF | HTML

LMK5C33216

활성

데이터 시트

지금 주문하기

제품 상세 정보

Function

Clock network synchronizer

Number of outputs

16

Output type

CML, LVCMOS, LVDS, LVPECL

RMS jitter (fs)

50

Features

JESD204B

Output frequency (min) (MHz)

0.000000000001

Output frequency (max) (MHz)

3000

Input type

HCSL, LVCMOS, LVDS, LVPECL, XTAL

Operating temperature range (°C)

-40 to 85

Number of input channels

2

Function

Clock network synchronizer

Number of outputs

16

Output type

CML, LVCMOS, LVDS, LVPECL

RMS jitter (fs)

50

Features

JESD204B

Output frequency (min) (MHz)

0.000000000001

Output frequency (max) (MHz)

3000

Input type

HCSL, LVCMOS, LVDS, LVPECL, XTAL

Operating temperature range (°C)

-40 to 85

Number of input channels

2

VQFN (RGC)

64

81 mm² (9 mm × 9 mm)

BAW APLL with 40 fs RMS jitter at 491.52 MHz
Three high-performance digital phase locked loops (DPLLs) with paired analog phase locked loops (APLLs)
- Programmable DPLL loop bandwidth from 0.01 Hz to 4 kHz
- -116 dBc/Hz at 100 Hz offset at 122.88 MHz DPLL TDC noise with ≥ 20 MHz TDC rate
Two differential or single-ended DPLL inputs
- 1 Hz to 800 MHz differential
- Hitless switching with phase cancellation and/or phase slew control
- Priority based reference selection
16 outputs with programmable format
- 1000 MHz LVPECL/LVDS/HSDS
- 3000 MHz CML on OUT4 and OUT6
- 200 MHz LVCMOS on OUT0 and OUT1
Single 3.3-V supply with internal LDOs
I²C or 3-wire/4-wire SPI interface
Requires single XO/TCXO/OCXO
40-bit DPLL or APLL DCO, < 1 ppt
Holdover with phase build out upon exit
Zero delay mode with programmable delay
User programmable EEPROM
Supports 105 °C PCB temperature

BAW APLL with 40 fs RMS jitter at 491.52 MHz
Three high-performance digital phase locked loops (DPLLs) with paired analog phase locked loops (APLLs)
- Programmable DPLL loop bandwidth from 0.01 Hz to 4 kHz
- -116 dBc/Hz at 100 Hz offset at 122.88 MHz DPLL TDC noise with ≥ 20 MHz TDC rate
Two differential or single-ended DPLL inputs
- 1 Hz to 800 MHz differential
- Hitless switching with phase cancellation and/or phase slew control
- Priority based reference selection
16 outputs with programmable format
- 1000 MHz LVPECL/LVDS/HSDS
- 3000 MHz CML on OUT4 and OUT6
- 200 MHz LVCMOS on OUT0 and OUT1
Single 3.3-V supply with internal LDOs
I²C or 3-wire/4-wire SPI interface
Requires single XO/TCXO/OCXO
40-bit DPLL or APLL DCO, < 1 ppt
Holdover with phase build out upon exit
Zero delay mode with programmable delay
User programmable EEPROM
Supports 105 °C PCB temperature

The LMK5C33216 is a high-performance network clock generator, synchronizer, and jitter attenuator with advanced reference clock selection and hitless switching capabilities designed to meet the stringent requirements of communications infrastructure applications.

The LMK5C33216 integrates 3 DPLLs with programmable loop bandwidth and no external loop filters, maximizing flexibility and ease of use. Each DPLL phase locks a paired APLL to a DPLL reference input. The APLL reference determines the long term frequency accuracy.

The 3 APLLs may operate independent of their paired DPLL and be cascaded from another APLL to provide programmable frequency translation. APLL3 features ultra high performance PLL with TI’s proprietary Bulk Acoustic Wave (BAW) VCBO technology and can generate output clocks with 40-fs RMS jitter independent of the jitter and frequency of the XO and reference inputs. APLL1 and APLL2 provide options for additional frequency domains.

The device is fully programmable through I²C or SPI interface. The onboard EEPROM can be used to customize system start-up clocks.

The LMK5C33216 is a high-performance network clock generator, synchronizer, and jitter attenuator with advanced reference clock selection and hitless switching capabilities designed to meet the stringent requirements of communications infrastructure applications.

The LMK5C33216 integrates 3 DPLLs with programmable loop bandwidth and no external loop filters, maximizing flexibility and ease of use. Each DPLL phase locks a paired APLL to a DPLL reference input. The APLL reference determines the long term frequency accuracy.

The 3 APLLs may operate independent of their paired DPLL and be cascaded from another APLL to provide programmable frequency translation. APLL3 features ultra high performance PLL with TI’s proprietary Bulk Acoustic Wave (BAW) VCBO technology and can generate output clocks with 40-fs RMS jitter independent of the jitter and frequency of the XO and reference inputs. APLL1 and APLL2 provide options for additional frequency domains.

The device is fully programmable through I²C or SPI interface. The onboard EEPROM can be used to customize system start-up clocks.

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4개 모두 보기

상위 문서	유형	직함	형식 옵션	날짜
*	데이터 시트	LMK5C33216 Ultra-Low Jitter Clock Synchronizer with JESD204B for Wireless Communications with BAW datasheet (Rev. B)	PDF \| HTML	2021. 3. 10
	애플리케이션 노트	Termination Guidelines for Differential and Single-Ended Signals	PDF \| HTML	2025. 12. 10
	애플리케이션 노트	ITU-T G.8262 Compliance Test Results for the LMK5C33216	PDF \| HTML	2020. 12. 23
	사용 설명서	LMK5C33216 Programming Guide	PDF \| HTML	2020. 12. 18

설계 및 개발

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평가 보드

LMK5C33216EVM — LMK5C33216 클록 싱크로나이저 DPLL 2 입력 16 출력 평가 모듈

LMK5C33216EVM은 LMK5C33216 네트워크 클록 제너레이터 및 싱크로나이저에 대한 평가 모듈(EVM)입니다. 이 EVM은 장치 평가, 규정 준수 테스트 및 시스템 프로토타이핑에 활용할 수 있습니다. LMK5C33216는 3개의 아날로그 PLL(APLL) 및 3개의 디지털 PLL(DPLL)을 프로그래머블 루프 대역폭에 결합합니다. EVM에는 50-Ω 테스트 장비와 장치를 상호 작용하기 위한 클록 입력, 오실레이터 입력 및 클록 출력을 위한 SMA 커넥터가 포함되어 있습니다. 온보드 TCXO를 이용하면 (...)

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지원 소프트웨어

TICSPRO-SW — TICS Pro GUI and Live Programming Tool for Clocking Devices

텍사스 인스트루먼트 클록 및 신시사이저(TICS) Pro 소프트웨어는 다음 접두사를 사용하여 제품 번호의 평가 모듈(EVM)을 프로그래밍하는 데 사용됩니다. CDC, LMK 및 LMX. 이러한 제품에는 위상 동기 루프 및 전압 제어 오실레이터(PLL+VCO), 신시사이저 및 클로킹 디바이스가 포함되어 있습니다.

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