SN65LVDS152
- A Member of the MuxIt Serializer-
Deserializer Building-Block Chip Family - Supports Deserialization of One Serial Link Data Channel Input at Rates up to 200 Mbps
- PLL Lock/Valid Input Provided to Enable Parallel Data and Clock Outputs
- Cascadable With Additional SN65LVDS152 MuxIt Receiver-Deserializers for Wider
Parallel Output Data Channel Widths - LVDS Compatible Differential Inputs and Outputs Meet or Exceed the Requirements
of ANSI TIA/EIA-644-A - LVDS Input and Output ESD Protection Exceeds 12 kV HBM
- LVTTL Compatible Inputs for Lock/Valid and Enables Are 5-V Tolerant
- Operates With 3.3-V Supply
- Packaged in 32-Pin DA Thin Shrink Small-Outline Package With 26-Mil
Terminal Pitch
MuxIt is a family of general-purpose, multiple-chip building blocks for implementing parallel data serializers and deserializers. The system allows for wide parallel data to be transmitted through a reduced number of transmission lines over distances greater than can be achieved with a single-ended (e.g., LVTTL or LVCMOS) data interface. The number of bits multiplexed per transmission line is user selectable, allowing for higher transmission efficiencies than with other existing fixed ratio solutions. MuxIt utilizes the LVDS (TIA/EIA-644-A) low voltage differential signaling technology for communications between the data source and data destination.
The MuxIt family initially includes three devices supporting simplex communications: the SN65LVDS150 phase locked loop frequency multiplier, the SN65LVDS151 serializer-transmitter, and the SN65LVDS152 receiver-deserializer.
The SN65LVDS152 consists of three LVDS differential transmission line receivers, an LVDS differential transmission line driver, a 10-bit serial-in/parallel-out shift register, plus associated input and output buffers. It receives serialized data over an LVDS transmission line link, deserializes (demultiplexes) it, and delivers it on parallel data outputs, DO–0 through DO–9. Data received over the link is clocked at a factor of M times the original parallel data frequency. The multiplexing ratio M, or number of bits per data clock cycle, is programmed with configuration pins (M1 → M5) on the companion SN65LVDS150 MuxIt programmable PLL frequency multiplier. Up to 10 bits of data may be deserialized and output by each SN65LVDS152. Two or more SN65LVDS152 units may be connected in series (cascaded) to accommodate wider parallel data paths for higher serialization values. The range of multiplexing ratio M supported by the SN65LVDS150 MuxIt programmable PLL frequency multiplier is between 4 and 40. shows some of the combinations of LCI and MCI supported by the SN65LVDS150 MuxIt programmable PLL frequency multiplier.
Data is serially shifted into the SN65LVDS152 shift register on the falling edges of the M-clock input (MCI). The data is latched out in parallel from the SN65LVDS152 shift register on the second rising edge after the first falling edge of the M-clock following a rising edge of the link clock input (LCI). The SN65LVDS152 includes LVDS differential line receivers for both the serialized link data stream (DI) and link clock (LCI). High-speed signals from the SN65LVDS150 MuxIt programmable frequency multiplier (MCI), plus the input and output for cascaded data (DI, CO) are carried over differential connections to minimize skew and jitter.
The enable input (EN) along with internal power-on reset (POR) controls the outputs. When Vcc is below 1.5 volts, or when EN is low, outputs are disabled. When VCC is above 3 V and EN is high, outputs are enabled and operating to specifications.
Parallel data bits are output from DO-n outputs in an order dependent on the value of the multiplexing ratio (frequency multiplier value) M. For values of M from 4 through 10, the cascade output (CO±) is not used, and only the top M parallel outputs (DO–9 through DO–[10-M]) are used. The data bit output on DO-9 corresponds to the data bit input on DI–[M–1] of the SN65LVDS151 serializer. Likewise, the data bit output on DO-[10-M] will correspond to the data bit input on DI–0 of the SN65LVDS151 serializer.
For values of M greater than 10, the cascade output (CO±) is used to connect multiple SN65LVDS152 deserializers. In this case the higher-order unit(s) output 10 bits each of the highest numbered bits that are input into the SN65LVDS151 serializer(s). The lowest numbered input bits are output on the lowest-order SN65LVDS152 deserializer in descending order from output DO–9. The number of bits is equal to M mod(10). reflects this information, where X = M mod(10)
Additional information on output bit ordering in cascaded applications can be found in the MuxIt Application Report.
기술 자료
유형 | 직함 | 날짜 | ||
---|---|---|---|---|
* | Data sheet | Muxit | 2011/09/16 | |
Application note | Performance of MuxIt(TM) with Different Cable Lengths | 2001/07/20 | ||
EVM User's guide | MuxIt | 2001/01/23 | ||
Application note | The MuxIt Data Transmission System Applications, Examples, and Design Guidelines | 2000/12/19 |
설계 및 개발
추가 조건 또는 필수 리소스는 사용 가능한 경우 아래 제목을 클릭하여 세부 정보 페이지를 확인하세요.
PSPICE-FOR-TI — TI 설계 및 시뮬레이션 툴용 PSpice®
TI 설계 및 시뮬레이션 환경용 PSpice는 기본 제공 라이브러리를 이용해 복잡한 혼합 신호 설계를 시뮬레이션할 수 있습니다. 레이아웃 및 제작에 (...)
TINA-TI — SPICE 기반 아날로그 시뮬레이션 프로그램
패키지 | 핀 | CAD 기호, 풋프린트 및 3D 모델 |
---|---|---|
TSSOP (DA) | 32 | Ultra Librarian |
주문 및 품질
- RoHS
- REACH
- 디바이스 마킹
- 납 마감/볼 재질
- MSL 등급/피크 리플로우
- MTBF/FIT 예측
- 물질 성분
- 인증 요약
- 지속적인 신뢰성 모니터링
- 팹 위치
- 조립 위치