SN65LVDS20
- Low-Voltage PECL Input and Low-Voltage PECL or LVDS Outputs
- Signaling Rates to 4 Gbps or Clock Rates to 2 GHz
- 120-ps Output Transition Times
- Less than 45 ps Total Jitter
- Less than 630 ps Propagation Delay Times
- 2.5-V or 3.3-V Supply Operation
- 2-mm x 2-mm Small-Outline No-Lead Package
- APPLICATIONS
- PECL-to-LVDS Translation
- Data or Clock Signal Amplification
The SN65LVDS20 and SN65LVP20 are a high-speed differential receiver and driver connected as a repeater. The receiver accepts low-voltage positive-emitter-coupled logic (PECL) at signaling rates up to 4 Gbps and repeats it as either an LVDS or PECL output signal. The signal path through the device is differential for low radiated emissions and minimal added jitter.
The outputs of the SN65LVDS20 are LVDS levels as defined by TIA/EIA-644-A. The outputs of the SN65LVDP20 are compatible with low-voltage PECL levels. A low-level input to EN enables the outputs. A high-level input puts the output into a high-impedance state. Both outputs are designed to drive differential transmission lines with nominally 100-
characteristic impedance.
Both devices provide a voltage reference (VBB) of typically 1.35 V below VCC for use in receiving single-ended PECL input signals. When not used, VBB should be unconnected or open.
All devices are characterized for operation from -40°C to 85°C.
기술 문서
| 유형 | 직함 | 날짜 | ||
|---|---|---|---|---|
| * | Data sheet | LVPECL and LVS Repeater/Translator With Enable datasheet (Rev. A) | 2005/09/13 | |
| Application brief | LVDS to Improve EMC in Motor Drives | 2018/09/27 | ||
| Application brief | How Far, How Fast Can You Operate LVDS Drivers and Receivers? | 2018/08/03 | ||
| Application brief | How to Terminate LVDS Connections with DC and AC Coupling | 2018/05/16 | ||
| EVM User's guide | Translator/Oscillator Buffer EVM (Rev. A) | 2004/09/17 |
설계 및 개발
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SN65LVDS20EVM — SN65LVDS20 평가 모듈
This Evaluation Module (EVM) facilitates the experimental testing of the Texas Instruments SN65LVDS20 Repeater/Translator silicon device.This device accepts low-voltage PECL input levels and Translates them to LVDS output levels as defined by TIA/EIA-644-A standard.
The device operates at rates to (...)
PSPICE-FOR-TI — TI 설계 및 시뮬레이션 툴용 PSpice®
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TINA-TI — SPICE 기반 아날로그 시뮬레이션 프로그램
| 패키지 | 핀 | 다운로드 |
|---|---|---|
| WSON (DRF) | 8 | 옵션 보기 |
주문 및 품질
- RoHS
- REACH
- 디바이스 마킹
- 납 마감/볼 재질
- MSL 등급/피크 리플로우
- MTBF/FIT 예측
- 물질 성분
- 인증 요약
- 지속적인 신뢰성 모니터링
- 팹 위치
- 조립 위치
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