홈 인터페이스 LVDS, M-LVDS 및 PECL
홈
인터페이스
LVDS, M-LVDS 및 PECL

SN65MLVD128

활성

1:8 LVTTL-M-LVDS 리피터

지금 주문
데이터시트

SN65MLVD128

활성
데이터시트 지금 주문

제품 상세 정보

Function Repeater, Translator Protocols M-LVDS Number of transmitters 8 Number of receivers 1 Supply voltage (V) 3.3 Signaling rate (MBits) 250 Input signal M-LVDS Output signal M-LVDS Rating Catalog Operating temperature range (°C) -40 to 85
Function Repeater, Translator Protocols M-LVDS Number of transmitters 8 Number of receivers 1 Supply voltage (V) 3.3 Signaling rate (MBits) 250 Input signal M-LVDS Output signal M-LVDS Rating Catalog Operating temperature range (°C) -40 to 85
TSSOP (DGG) 48 101.25 mm² 12.5 x 8.1
  • LVTTL Receiver and Eight Line Drivers Configured as an 8-Port M-LVDS Repeater—SN65MLVD128
  • 2 LVTTL Receivers and Eight Line Drivers Configured as Dual 4-Port M-LVDS Repeaters—SN65MLVD129
  • Drivers Meet or Exceed the M-LVDS Standard (TIA/EIA-899)
  • Low-Voltage Differential 30- Line Drivers for Data Rates¹ Up to 250 Mbps or Clock Frequencies Up to 125 MHz
  • Power Up/Down Glitch Free
  • Controlled Driver Output Voltage Transition Times for Improved Signal Quality
  • Bus Pins High Impedance When Disabled or VCC ≤ 1.5 V
  • Independent Enables for each Driver
  • Output-to-Ouput Skew tsk(o) ≤ 160 ps
       Part-to-Part Skew tsk(pp) ≤ 800 ps
  • Single 3.3-V Voltage Supply
  • Bus Pin ESD Protection Exceeds 9 kV
  • Packaged in 48-Pin TSSOP (DGG)
  • APPLICATIONS
    • AdvancedTCA™ (ATCA™) Clock Bus Driver
    • Clock Distribution
    • Data and Clock Repeating Over Backplanes and Cables
    • Cellular Base Stations
    • Central Office Switches
    • Network Switches and Routers

¹The data rate of a line, is the number of voltage transitions that are made per second expressed in the units bps (bits per second).
AdvancedTCA and ATCA are trademarks of the PCI Industrial Computer Manufacturers Group.
  • LVTTL Receiver and Eight Line Drivers Configured as an 8-Port M-LVDS Repeater—SN65MLVD128
  • 2 LVTTL Receivers and Eight Line Drivers Configured as Dual 4-Port M-LVDS Repeaters—SN65MLVD129
  • Drivers Meet or Exceed the M-LVDS Standard (TIA/EIA-899)
  • Low-Voltage Differential 30- Line Drivers for Data Rates¹ Up to 250 Mbps or Clock Frequencies Up to 125 MHz
  • Power Up/Down Glitch Free
  • Controlled Driver Output Voltage Transition Times for Improved Signal Quality
  • Bus Pins High Impedance When Disabled or VCC ≤ 1.5 V
  • Independent Enables for each Driver
  • Output-to-Ouput Skew tsk(o) ≤ 160 ps
       Part-to-Part Skew tsk(pp) ≤ 800 ps
  • Single 3.3-V Voltage Supply
  • Bus Pin ESD Protection Exceeds 9 kV
  • Packaged in 48-Pin TSSOP (DGG)
  • APPLICATIONS
    • AdvancedTCA™ (ATCA™) Clock Bus Driver
    • Clock Distribution
    • Data and Clock Repeating Over Backplanes and Cables
    • Cellular Base Stations
    • Central Office Switches
    • Network Switches and Routers

¹The data rate of a line, is the number of voltage transitions that are made per second expressed in the units bps (bits per second).
AdvancedTCA and ATCA are trademarks of the PCI Industrial Computer Manufacturers Group.

The SN65MLVD128 and SN65MLVD129 are LVTTL-to-M.LVDS translators/repeaters. Outputs comply with the M.LVDS standard (TIA/EIA-899) and are optimized for data rates up to 250 Mbps, and clock frequencies up to 125 MHz. The driver outputs have been designed to support multipoint buses presenting loads as low as 30 and incorporates controlled transition times for backbone operation.

M-LVDS compliant devices allow for 32 nodes on a common bus, providing a high-speed replacement for RS-485 devices when lower common-mode voltage range and lower output signaling levels are acceptable. The SN65MLVD128 and SN65MLVD129 provide separate driver enables, allowing for independent control of each output signal.

Intended applications for these devices include transmission of clock signals from a central clock module, as well as translation and buffering of data or control signals for transmission through a controlled impedance backplane or cable.

The SN65MLVD128 and SN65MLVD129 are LVTTL-to-M.LVDS translators/repeaters. Outputs comply with the M.LVDS standard (TIA/EIA-899) and are optimized for data rates up to 250 Mbps, and clock frequencies up to 125 MHz. The driver outputs have been designed to support multipoint buses presenting loads as low as 30 and incorporates controlled transition times for backbone operation.

M-LVDS compliant devices allow for 32 nodes on a common bus, providing a high-speed replacement for RS-485 devices when lower common-mode voltage range and lower output signaling levels are acceptable. The SN65MLVD128 and SN65MLVD129 provide separate driver enables, allowing for independent control of each output signal.

Intended applications for these devices include transmission of clock signals from a central clock module, as well as translation and buffering of data or control signals for transmission through a controlled impedance backplane or cable.
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기술 문서

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모두 보기4
유형 직함 날짜
* Data sheet SN65MLVD128/129 - 1:8 LVTTL to M-LVDS Repeater, Dual 1:4 LVTTL to M-LVDS Repeate datasheet 2003/09/04
Application note An Introduction to M-LVDS and Clock and Data Distribution Applications (Rev. C) PDF | HTML 2023/06/22
Application brief How Far, How Fast Can You Operate MLVDS? 2018/08/06
Application note SPI-Based Data Acquisition/Monitor Using the TLC2551 Serial ADC (Rev. A) 2001/11/20

설계 및 개발

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시뮬레이션 모델

SN65MLVD128 IBIS Model

SLLC206.ZIP (8 KB) - IBIS Model
다운로드
시뮬레이션 툴

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TINA-TI provides all the conventional DC, transient and frequency domain analysis of SPICE and much more. TINA has extensive post-processing capability that allows you to format results the way you want them. Virtual instruments allow you to select input waveforms and probe circuit nodes voltages (...)
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옵션 보기
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TSSOP (DGG) 48 옵션 보기
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주문 및 품질

포함된 정보:
  • RoHS
  • REACH
  • 디바이스 마킹
  • 납 마감/볼 재질
  • MSL 등급/피크 리플로우
  • MTBF/FIT 예측
  • 물질 성분
  • 인증 요약
  • 지속적인 신뢰성 모니터링
포함된 정보:
  • 팹 위치
  • 조립 위치

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