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SN74LVCC4245A

활성

조정 가능 출력 전압 및 3상 출력을 지원하는 8진 버스 트랜시버

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데이터 시트

SN74LVCC4245A

활성
데이터 시트 지금 주문하기

제품 상세 정보

Bits (#) 8 Data rate (max) (Mbps) 200 Topology Push-Pull Vin (min) (V) 4.5 Vin (max) (V) 5.5 Vout (min) (V) 2.7 Vout (max) (V) 5.5 Applications GPIO, JTAG, SPI, UART Features Output enable Prop delay (ns) 7 Technology family LVC Supply current (max) (mA) 0.16 Rating Catalog Operating temperature range (°C) -40 to 85
Bits (#) 8 Data rate (max) (Mbps) 200 Topology Push-Pull Vin (min) (V) 4.5 Vin (max) (V) 5.5 Vout (min) (V) 2.7 Vout (max) (V) 5.5 Applications GPIO, JTAG, SPI, UART Features Output enable Prop delay (ns) 7 Technology family LVC Supply current (max) (mA) 0.16 Rating Catalog Operating temperature range (°C) -40 to 85
SOIC (DW) 24 159.65 mm² 15.5 x 10.3 SOP (NS) 24 117 mm² 15 x 7.8 SSOP (DB) 24 63.96 mm² 8.2 x 7.8 TSSOP (PW) 24 49.92 mm² 7.8 x 6.4
  • 8-bit direction controlled translating bus transceiver
  • 4.5V to 5.5V on A port and 2.7V to 5.5V on B port
  • Robust, glitch-free power supply sequencing
  • VCC isolation and VCC disconnect feature
    • If either VCC input is below 100mV or left floating, all I/O outputs are disabled and become high impedance
  • Control inputs VIH and VIL levels are referenced to VCCA voltage
  • High drive strength for heavier loads: 24mA drive at 3V supply
  • Latch-up performance exceeds 250mA per JESD 17
  • Operating temperature range -40°C to 85°C
  • ESD protection exceeds JESD 22
    • 2000V Human-Body Model (A114-A)
    • 1000V Charged-Device Model (C101)
  • Compatible with SN74LVC4245
  • 8-bit direction controlled translating bus transceiver
  • 4.5V to 5.5V on A port and 2.7V to 5.5V on B port
  • Robust, glitch-free power supply sequencing
  • VCC isolation and VCC disconnect feature
    • If either VCC input is below 100mV or left floating, all I/O outputs are disabled and become high impedance
  • Control inputs VIH and VIL levels are referenced to VCCA voltage
  • High drive strength for heavier loads: 24mA drive at 3V supply
  • Latch-up performance exceeds 250mA per JESD 17
  • Operating temperature range -40°C to 85°C
  • ESD protection exceeds JESD 22
    • 2000V Human-Body Model (A114-A)
    • 1000V Charged-Device Model (C101)
  • Compatible with SN74LVC4245

This 8-bit (octal) noninverting bus transceiver uses two separate power-supply rails. The A port, VCCA, is dedicated to accepting a 5V supply level, and the configurable B port, which is designed to track VCCB, accepts voltages from 3V to 5V. This allows for translation from a 3.3V to a 5V environment and vice versa.

The SN74LVCC4245A device is designed for asynchronous communication between data buses. The SN74LVCC4245A device transmits data from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at the direction-control (DIR) input. The output-enable (OE) input can be used to disable the device so the buses effectively are isolated. The control circuitry (DIR, OE) is powered by VCCA.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. The VCC isolation feature is designed so that if either VCCA or VCCB is less than 100mV, both I/O ports enter a high-impedance state by disabling their outputs.

This 8-bit (octal) noninverting bus transceiver uses two separate power-supply rails. The A port, VCCA, is dedicated to accepting a 5V supply level, and the configurable B port, which is designed to track VCCB, accepts voltages from 3V to 5V. This allows for translation from a 3.3V to a 5V environment and vice versa.

The SN74LVCC4245A device is designed for asynchronous communication between data buses. The SN74LVCC4245A device transmits data from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at the direction-control (DIR) input. The output-enable (OE) input can be used to disable the device so the buses effectively are isolated. The control circuitry (DIR, OE) is powered by VCCA.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. The VCC isolation feature is designed so that if either VCCA or VCCB is less than 100mV, both I/O ports enter a high-impedance state by disabling their outputs.
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기술 자료

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31개 모두 보기
상위 문서 유형 직함 형식 옵션 날짜
* Data sheet SN74LVCC4245A Octal Dual-Supply Bus Transceiver With Configurable Output Voltage and 3-State Outputs datasheet (Rev. O) PDF | HTML 2026/05/29
Selection guide Logic Guide (Rev. AC) PDF | HTML 2025/11/13
Application note Schematic Checklist - A Guide to Designing With Fixed or Direction Control Translators PDF | HTML 2024/10/02
Application note Schematic Checklist - A Guide to Designing with Auto-Bidirectional Translators PDF | HTML 2024/07/12
Application note Understanding Transient Drive Strength vs. DC Drive Strength in Level-Shifters (Rev. A) PDF | HTML 2024/07/03
Application note Implications of Slow or Floating CMOS Inputs (Rev. E) 2021/07/26
Selection guide Voltage Translation Buying Guide (Rev. A) 2021/04/15
Selection guide Little Logic Guide 2018 (Rev. G) 2018/07/06
Application note How to Select Little Logic (Rev. A) 2016/07/26
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 2015/12/02
User guide LOGIC Pocket Data Book (Rev. B) 2007/01/16
Product overview Design Summary for WCSP Little Logic (Rev. B) 2004/11/04
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 2004/07/08
Application note Selecting the Right Level Translation Solution (Rev. A) 2004/06/22
User guide Signal Switch Data Book (Rev. A) 2003/11/14
Application note Use of the CMOS Unbuffered Inverter in Oscillator Circuits 2003/11/06
User guide LVC and LV Low-Voltage CMOS Logic Data Book (Rev. B) 2002/12/18
Application note Texas Instruments Little Logic Application Report 2002/11/01
Application note TI IBIS File Creation, Validation, and Distribution Processes 2002/08/29
More literature Standard Linear & Logic for PCs, Servers & Motherboards 2002/06/13
Application note 16-Bit Widebus Logic Families in 56-Ball, 0.65-mm Pitch Very Thin Fine-Pitch BGA (Rev. B) 2002/05/22
Application note Power-Up 3-State (PU3S) Circuits in TI Standard Logic Devices 2002/05/10
More literature STANDARD LINEAR AND LOGIC FOR DVD/VCD PLAYERS 2002/03/27
Application note Migration From 3.3-V To 2.5-V Power Supplies For Logic Devices 1997/12/01
Application note Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A) 1997/08/01
Application note CMOS Power Consumption and CPD Calculation (Rev. B) 1997/06/01
Application note LVC Characterization Information 1996/12/01
Application note Input and Output Characteristics of Digital Integrated Circuits 1996/10/01
Application note Live Insertion 1996/10/01
Design guide Low-Voltage Logic (LVC) Designer's Guide 1996/09/01
Application note Understanding Advanced Bus-Interface Products Design Guide 1996/05/01

설계 및 개발

추가 조건 또는 필수 리소스는 사용 가능한 경우 아래 제목을 클릭하여 세부 정보 페이지를 확인하세요.

평가 보드

14-24-LOGIC-EVM — 14핀~24핀 D, DB, DGV, DW, DYY, NS 및 PW 패키지용 로직 제품 일반 평가 모듈

14-24-LOGIC-EVM 평가 모듈(EVM)은 14핀~24핀 D, DW, DB, NS, PW, DYY 또는 DGV 패키지에 있는 모든 로직 장치를 지원하도록 설계되었습니다.

사용 설명서: PDF | HTML
TI.com에서 구매할 수 없음
평가 보드

AVCLVCDIRCNTRL-EVM — AVC 및 LVC를 지원하는 방향 제어 양방향 변환 디바이스를 위한 일반 EVM

일반 EVM은 2개, 4개 및 8개 채널 LVC 및 AVC 방향 제어 변환 장치를 지원하도록 설계했습니다. 또한 동일한 개수의 채널에서 버스 홀드 및 차량용 -Q1 장치를 지원합니다. AVC는 구동 강도가 더 낮은 12mA인 저전압 변환 장치입니다. LVC는 구동 강도가 더 높은 32mA로, 1.65~5.5V의 더 높은 전압 변환 장치입니다.

사용 설명서: PDF
TI.com에서 구매할 수 없음
시뮬레이션 모델

SN74LVCC4245A IBIS Model

SCAM034.ZIP (43 KB) - IBIS Model
다운로드
패키지 핀 CAD 기호, 풋프린트 및 3D 모델
SOIC (DW) 24 Ultra Librarian
SOP (NS) 24 Ultra Librarian
SSOP (DB) 24 Ultra Librarian
TSSOP (PW) 24 Ultra Librarian
TI의 평가 항목에 대한 표준 약관이 적용됩니다.

주문 및 품질

포함된 정보:
  • RoHS
  • REACH
  • 디바이스 마킹
  • 납 마감/볼 재질
  • MSL 등급/피크 리플로우
  • MTBF/FIT 예측
  • 물질 성분
  • 인증 요약
  • 지속적인 신뢰성 모니터링
포함된 정보:
  • 팹 위치
  • 조립 위치

지원 및 교육

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포럼 주제 모두 보기(영문)

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