SN74LVCC4245A

활성

조정 가능 출력 전압 및 3상 출력을 지원하는 8진 버스 트랜시버

제품 상세 정보

Bits (#) 8 Data rate (max) (Mbps) 200 Topology Push-Pull Vin (min) (V) 4.5 Vin (max) (V) 5.5 Vout (min) (V) 2.7 Vout (max) (V) 5.5 Applications GPIO, JTAG, SPI, UART Features Output enable Prop delay (ns) 7 Technology family LVC Supply current (max) (mA) 0.16 Rating Catalog Operating temperature range (°C) -40 to 85
Bits (#) 8 Data rate (max) (Mbps) 200 Topology Push-Pull Vin (min) (V) 4.5 Vin (max) (V) 5.5 Vout (min) (V) 2.7 Vout (max) (V) 5.5 Applications GPIO, JTAG, SPI, UART Features Output enable Prop delay (ns) 7 Technology family LVC Supply current (max) (mA) 0.16 Rating Catalog Operating temperature range (°C) -40 to 85
TSSOP (PW) 24 49.92 mm² (7.8 mm × 6.4 mm) SSOP (DB) 24 63.96 mm² (8.2 mm × 7.8 mm) SOIC (DW) 24 159.65 mm² (15.5 mm × 10.3 mm) SOP (NS) 24 117 mm² (15 mm × 7.8 mm)
  • 8-bit direction controlled translating bus transceiver
  • 4.5V to 5.5V on A port and 2.7V to 5.5V on B port
  • Robust, glitch-free power supply sequencing
  • VCC isolation and VCC disconnect feature
    • If either VCC input is below 100mV or left floating, all I/O outputs are disabled and become high impedance
  • Control inputs VIH and VIL levels are referenced to VCCA voltage
  • High drive strength for heavier loads: 24mA drive at 3V supply
  • Latch-up performance exceeds 250mA per JESD 17
  • Operating temperature range -40°C to 85°C
  • ESD protection exceeds JESD 22
    • 2000V Human-Body Model (A114-A)
    • 1000V Charged-Device Model (C101)
  • Compatible with SN74LVC4245
  • 8-bit direction controlled translating bus transceiver
  • 4.5V to 5.5V on A port and 2.7V to 5.5V on B port
  • Robust, glitch-free power supply sequencing
  • VCC isolation and VCC disconnect feature
    • If either VCC input is below 100mV or left floating, all I/O outputs are disabled and become high impedance
  • Control inputs VIH and VIL levels are referenced to VCCA voltage
  • High drive strength for heavier loads: 24mA drive at 3V supply
  • Latch-up performance exceeds 250mA per JESD 17
  • Operating temperature range -40°C to 85°C
  • ESD protection exceeds JESD 22
    • 2000V Human-Body Model (A114-A)
    • 1000V Charged-Device Model (C101)
  • Compatible with SN74LVC4245

This 8-bit (octal) noninverting bus transceiver uses two separate power-supply rails. The A port, VCCA, is dedicated to accepting a 5V supply level, and the configurable B port, which is designed to track VCCB, accepts voltages from 3V to 5V. This allows for translation from a 3.3V to a 5V environment and vice versa.

The SN74LVCC4245A device is designed for asynchronous communication between data buses. The SN74LVCC4245A device transmits data from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at the direction-control (DIR) input. The output-enable (OE) input can be used to disable the device so the buses effectively are isolated. The control circuitry (DIR, OE) is powered by VCCA.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. The VCC isolation feature is designed so that if either VCCA or VCCB is less than 100mV, both I/O ports enter a high-impedance state by disabling their outputs.

This 8-bit (octal) noninverting bus transceiver uses two separate power-supply rails. The A port, VCCA, is dedicated to accepting a 5V supply level, and the configurable B port, which is designed to track VCCB, accepts voltages from 3V to 5V. This allows for translation from a 3.3V to a 5V environment and vice versa.

The SN74LVCC4245A device is designed for asynchronous communication between data buses. The SN74LVCC4245A device transmits data from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at the direction-control (DIR) input. The output-enable (OE) input can be used to disable the device so the buses effectively are isolated. The control circuitry (DIR, OE) is powered by VCCA.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. The VCC isolation feature is designed so that if either VCCA or VCCB is less than 100mV, both I/O ports enter a high-impedance state by disabling their outputs.

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기술 자료

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* 데이터 시트 SN74LVCC4245A Octal Dual-Supply Bus Transceiver With Configurable Output Voltage and 3-State Outputs datasheet (Rev. O) PDF | HTML 2026. 5. 29
애플리케이션 노트 Schematic Checklist - A Guide to Designing With Fixed or Direction Control Translators PDF | HTML 2024. 10. 2
애플리케이션 노트 Schematic Checklist - A Guide to Designing with Auto-Bidirectional Translators PDF | HTML 2024. 7. 12
애플리케이션 노트 Understanding Transient Drive Strength vs. DC Drive Strength in Level-Shifters (Rev. A) PDF | HTML 2024. 7. 3
선택 가이드 Voltage Translation Buying Guide (Rev. A) 2021. 4. 15

설계 및 개발

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평가 보드

14-24-LOGIC-EVM — 14핀~24핀 D, DB, DGV, DW, DYY, NS 및 PW 패키지용 로직 제품 일반 평가 모듈

14-24-LOGIC-EVM 평가 모듈(EVM)은 14핀~24핀 D, DW, DB, NS, PW, DYY 또는 DGV 패키지에 있는 모든 로직 장치를 지원하도록 설계되었습니다.

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평가 보드

AVCLVCDIRCNTRL-EVM — AVC 및 LVC를 지원하는 방향 제어 양방향 변환 디바이스를 위한 일반 EVM

일반 EVM은 2개, 4개 및 8개 채널 LVC 및 AVC 방향 제어 변환 장치를 지원하도록 설계했습니다. 또한 동일한 개수의 채널에서 버스 홀드 및 차량용 -Q1 장치를 지원합니다. AVC는 구동 강도가 더 낮은 12mA인 저전압 변환 장치입니다. LVC는 구동 강도가 더 높은 32mA로, 1.65~5.5V의 더 높은 전압 변환 장치입니다.

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시뮬레이션 모델

SN74LVCC4245A IBIS Model

SCAM034.ZIP (43 KB) - IBIS 모델
지원되는 제품 및 하드웨어
패키지 CAD 기호, 풋프린트 및 3D 모델
TSSOP (PW) 24 Ultra Librarian
SSOP (DB) 24 Ultra Librarian
SOIC (DW) 24 Ultra Librarian
SOP (NS) 24 Ultra Librarian

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