홈 마이크로컨트롤러(MCU) 및 프로세서 Arm 기반 프로세서
홈
마이크로컨트롤러(MCU) 및 프로세서
Arm 기반 프로세서

TMS320DM8127

활성

DaVinci 디지털 미디어 프로세서

지금 주문
데이터시트
사용 설명서
정오표

TMS320DM8127

활성
데이터시트 지금 주문

제품 상세 정보

Arm CPU 1 Arm Cortex-A8 Arm (max) (MHz) 1000 CPU 32-bit Display type 2 LCD Ethernet MAC 2-Port 10/100/1000 PCIe 1 PCIe Gen 2 Hardware accelerators Face Detect Rating Catalog Power supply solution TPS65050 Operating temperature range (°C) -40 to 90
Arm CPU 1 Arm Cortex-A8 Arm (max) (MHz) 1000 CPU 32-bit Display type 2 LCD Ethernet MAC 2-Port 10/100/1000 PCIe 1 PCIe Gen 2 Hardware accelerators Face Detect Rating Catalog Power supply solution TPS65050 Operating temperature range (°C) -40 to 90
FCBGA (CYE) 684 529 mm² 23 x 23
  • High-Performance DaVinci Video Processors
    • Up to 1-GHz ARM® Cortex®-A8 RISC Core
    • Up to 750-MHz C674x VLIW DSP
    • Up to 6000 MIPS and 4500 MFLOPS
    • Fully Software-Compatible with C67x+, C64x+
  • ARM Cortex-A8 Core
    • ARMv7 Architecture
      • In-Order, Dual-Issue, Superscalar Processor Core
      • Neon™ Multimedia Architecture
      • Supports Integer and Floating Point
      • Jazelle® RCT Execution Environment
  • ARM Cortex-A8 Memory Architecture
    • 32KB of Instruction and Data Caches
    • 256KB of L2 Cache
    • 64KB of RAM, 48KB of Boot ROM
  • TMS320C674x Floating-Point VLIW DSP
    • 64 General-Purpose Registers (32-Bit)
    • Six ALU (32-/40-Bit) Functional Units
      • Supports 32-Bit Integer, SP (IEEE Single Precision/32-Bit) and DP (IEEE Double Precision/64-Bit) Floating Point
      • Supports up to Four SP Adds Per Clock and Four DP Adds Every Two Clocks
      • Supports up to Two Floating-Point (SP or DP) Approximate Reciprocal or Square Root Operations Per Cycle
    • Two Multiply Functional Units
      • Mixed-Precision IEEE Floating-Point Multiply Supported up to:
        • 2 SP x SP → SP Per Clock
        • 2 SP x SP → DP Every Two Clocks
        • 2 SP x DP → DP Every Three Clocks
        • 2 DP x DP → DP Every Four Clocks
      • Fixed-Point Multiply Supports Two 32 x 32 Multiplies, Four 16 x 16-Bit Multiplies Including Complex Multiplies, or Eight 8 x 8-Bit Multiplies per Clock Cycle
  • 128KB of On-Chip Memory Controller (OCMC) RAM
  • Imaging Subsystem (ISS)
    • Camera Sensor Connection
      • Parallel Connection for Raw (up to 16-Bit) and BT.656 or BT.1120 (8- and 16-Bit)
      • CSI2 Serial Connection
    • Image Sensor Interface (ISIF) for Handling Image and Video Data From the Camera Sensor
    • Image Pipe Interface (IPIPEIF) for Image and Video Data Connection Between Camera Sensor, ISIF, IPIPE, and DRAM
    • Image Pipe (IPIPE) for Real-Time Image and Video Processing
    • Resizer
      • Resizing Image and Video From 1/16x to 8x
      • Generating Two Different Resizing Outputs Concurrently
    • Hardware 3A Engine (H3A) for Generating Key Statistics for 3A (AE, AWB, and AF) Control
  • Face Detect Engine (FD)
    • Hardware Face Detection for up to 35 Faces at OPP100
  • Programmable High-Definition Video Image Coprocessing (HDVICP v2) Engine
    • Encode, Decode, Transcode Operations
    • H.264, MPEG-2, VC-1, MPEG-4, SP/ASP, JPEG/MJPEG
  • Media Controller
    • Controls the HDVPSS and ISS
  • Endianness
    • ARM and DSP Instructions/Data – Little Endian
  • HD Video Processing Subsystem (HDVPSS)
    • One 165-MHz HD Video Capture Input
      • One 16- or 24-Bit Input, Splittable into Dual 8-Bit SD Capture Ports
    • Two 165-MHz HD Video Display Outputs
      • One 16-, 24-, or 30-Bit Output and One 16- or 24-Bit Output
    • Composite or S-Video Analog Output
    • Macrovision® Support Available
    • Digital HDMI 1.3 Transmitter With Integrated PHY
    • Advanced Video Processing Features Such as Scan, Format, Rate Conversion
    • Three Graphics Layers and Compositors
  • Dual 32-Bit DDR2/DDR3 SDRAM Interfaces
    • Supports up to DDR2-800 and DDR3-1066
    • Up to Eight x 8 Devices Total 2GB of Total Address Space
    • Dynamic Memory Manager (DMM)
      • Programmable Multi-Zone Memory Mapping and Interleaving
      • Enables Efficient 2D Block Accesses
      • Supports Tiled Objects in 0°, 90°, 180°, or 270° Orientation and Mirroring
      • Optimizes Interlaced Accesses
  • General-Purpose Memory Controller (GPMC)
    • 8- or 16-Bit Multiplexed Address and Data Bus
    • 512MB of Address Space Divided Among up to 8 Chip Selects
    • Glueless Interface to NOR Flash, NAND Flash (BCH/Hamming Error Code Detection), SRAM and Pseudo-SRAM
    • Error Locator Module (ELM) Outside of GPMC to Provide Up to 16-Bit or 512-Byte Hardware ECC for NAND
    • Flexible Asynchronous Protocol Control for Interface to FPGA, CPLD, ASICs, and so Forth
  • Enhanced Direct Memory Access (EDMA) Controller
    • Four Transfer Controllers
    • 64 Independent DMA Channels and 8 Independent QDMA Channels
  • Dual Port Ethernet (10/100/1000 Mbps) With Optional Switch
    • IEEE 802.3 Compliant (3.3-V I/O Only)
    • MII/RMII/GMII/RGMII Media Independent Interfaces
    • Management Data I/O (MDIO) Module
    • Reset Isolation
    • IEEE 1588 Time-Stamping, AVB, and Industrial Ethernet Protocols
  • Dual USB 2.0 Ports With Integrated PHYs
    • USB2.0 High- and Full-Speed Clients
    • USB2.0 High-, Full-, and Low-Speed Hosts, or OTG
    • Supports End Points 0–15
  • One PCI Express 2.0 Port With Integrated PHY
    • Single Port With One Lane at 5.0 GT/s
    • Configurable as Root Complex or Endpoint
  • Eight 32-Bit General-Purpose Timers (Timer1–8)
  • One System Watchdog Timer (WDT0)
  • Six Configurable UART/IrDA/CIR Modules
    • UART0 With Modem Control Signals
    • Supports up to 3.6864 Mbps UART0/1/2
    • Supports up to 12 Mbps UART3/4/5
    • SIR, MIR, FIR (4.0 MBAUD), and CIR
  • Four Serial Peripheral Interfaces (SPIs) (up to
    48 MHz)
    • Each With Four Chip Selects
  • Three MMC/SD/SDIO Serial Interfaces (up to
    48 MHz)
    • Three Supporting up to 1-, 4-, or 8-Bit Modes
  • Four Inter-Integrated Circuit (I2C Bus) Ports
  • Six Multichannel Audio Serial Ports (McASPs)
    • Dual Ten Serializer Transmit and Receive Ports
    • Quad Four Serializer Transmit and Receive Ports
    • DIT-Capable For S/PDIF (All Ports)
  • Multichannel Buffered Serial Port (McBSP)
    • Transmit and Receive Clocks up to 48 MHz
    • Two Clock Zones and Two Serial Data Pins
    • Supports TDM, I2S, and Similar Formats
  • Real-Time Clock (RTC)
    • One-Time or Periodic Interrupt Generation
  • Up to 128 General-Purpose I/O (GPIO) Pins
  • One Spin Lock Module with up to 128 Hardware Semaphores
  • One Mailbox Module with 12 Mailboxes
  • On-Chip ARM ROM Bootloader (RBL)
  • Power, Reset, and Clock Management
    • Multiple Independent Core Power Domains
    • Multiple Independent Core Voltage Domains
    • Support for Three Operating Points (OPP100, OPP120, OPP166) per Voltage Domain
    • Clock Enable and Disable Control for Subsystems and Peripherals
  • 32KB of Embedded Trace Buffer (ETB) and
    5-Pin Trace Interface for Debug
  • IEEE 1149.1 (JTAG) Compatible
  • 684-Pin Pb-Free BGA Package (CYE Suffix), 0.8-mm Ball Pitch With Via Channel Technology to Reduce PCB Cost
  • 45-nm CMOS Technology

    •  
  • High-Performance DaVinci Video Processors
    • Up to 1-GHz ARM® Cortex®-A8 RISC Core
    • Up to 750-MHz C674x VLIW DSP
    • Up to 6000 MIPS and 4500 MFLOPS
    • Fully Software-Compatible with C67x+, C64x+
  • ARM Cortex-A8 Core
    • ARMv7 Architecture
      • In-Order, Dual-Issue, Superscalar Processor Core
      • Neon™ Multimedia Architecture
      • Supports Integer and Floating Point
      • Jazelle® RCT Execution Environment
  • ARM Cortex-A8 Memory Architecture
    • 32KB of Instruction and Data Caches
    • 256KB of L2 Cache
    • 64KB of RAM, 48KB of Boot ROM
  • TMS320C674x Floating-Point VLIW DSP
    • 64 General-Purpose Registers (32-Bit)
    • Six ALU (32-/40-Bit) Functional Units
      • Supports 32-Bit Integer, SP (IEEE Single Precision/32-Bit) and DP (IEEE Double Precision/64-Bit) Floating Point
      • Supports up to Four SP Adds Per Clock and Four DP Adds Every Two Clocks
      • Supports up to Two Floating-Point (SP or DP) Approximate Reciprocal or Square Root Operations Per Cycle
    • Two Multiply Functional Units
      • Mixed-Precision IEEE Floating-Point Multiply Supported up to:
        • 2 SP x SP → SP Per Clock
        • 2 SP x SP → DP Every Two Clocks
        • 2 SP x DP → DP Every Three Clocks
        • 2 DP x DP → DP Every Four Clocks
      • Fixed-Point Multiply Supports Two 32 x 32 Multiplies, Four 16 x 16-Bit Multiplies Including Complex Multiplies, or Eight 8 x 8-Bit Multiplies per Clock Cycle
  • 128KB of On-Chip Memory Controller (OCMC) RAM
  • Imaging Subsystem (ISS)
    • Camera Sensor Connection
      • Parallel Connection for Raw (up to 16-Bit) and BT.656 or BT.1120 (8- and 16-Bit)
      • CSI2 Serial Connection
    • Image Sensor Interface (ISIF) for Handling Image and Video Data From the Camera Sensor
    • Image Pipe Interface (IPIPEIF) for Image and Video Data Connection Between Camera Sensor, ISIF, IPIPE, and DRAM
    • Image Pipe (IPIPE) for Real-Time Image and Video Processing
    • Resizer
      • Resizing Image and Video From 1/16x to 8x
      • Generating Two Different Resizing Outputs Concurrently
    • Hardware 3A Engine (H3A) for Generating Key Statistics for 3A (AE, AWB, and AF) Control
  • Face Detect Engine (FD)
    • Hardware Face Detection for up to 35 Faces at OPP100
  • Programmable High-Definition Video Image Coprocessing (HDVICP v2) Engine
    • Encode, Decode, Transcode Operations
    • H.264, MPEG-2, VC-1, MPEG-4, SP/ASP, JPEG/MJPEG
  • Media Controller
    • Controls the HDVPSS and ISS
  • Endianness
    • ARM and DSP Instructions/Data – Little Endian
  • HD Video Processing Subsystem (HDVPSS)
    • One 165-MHz HD Video Capture Input
      • One 16- or 24-Bit Input, Splittable into Dual 8-Bit SD Capture Ports
    • Two 165-MHz HD Video Display Outputs
      • One 16-, 24-, or 30-Bit Output and One 16- or 24-Bit Output
    • Composite or S-Video Analog Output
    • Macrovision® Support Available
    • Digital HDMI 1.3 Transmitter With Integrated PHY
    • Advanced Video Processing Features Such as Scan, Format, Rate Conversion
    • Three Graphics Layers and Compositors
  • Dual 32-Bit DDR2/DDR3 SDRAM Interfaces
    • Supports up to DDR2-800 and DDR3-1066
    • Up to Eight x 8 Devices Total 2GB of Total Address Space
    • Dynamic Memory Manager (DMM)
      • Programmable Multi-Zone Memory Mapping and Interleaving
      • Enables Efficient 2D Block Accesses
      • Supports Tiled Objects in 0°, 90°, 180°, or 270° Orientation and Mirroring
      • Optimizes Interlaced Accesses
  • General-Purpose Memory Controller (GPMC)
    • 8- or 16-Bit Multiplexed Address and Data Bus
    • 512MB of Address Space Divided Among up to 8 Chip Selects
    • Glueless Interface to NOR Flash, NAND Flash (BCH/Hamming Error Code Detection), SRAM and Pseudo-SRAM
    • Error Locator Module (ELM) Outside of GPMC to Provide Up to 16-Bit or 512-Byte Hardware ECC for NAND
    • Flexible Asynchronous Protocol Control for Interface to FPGA, CPLD, ASICs, and so Forth
  • Enhanced Direct Memory Access (EDMA) Controller
    • Four Transfer Controllers
    • 64 Independent DMA Channels and 8 Independent QDMA Channels
  • Dual Port Ethernet (10/100/1000 Mbps) With Optional Switch
    • IEEE 802.3 Compliant (3.3-V I/O Only)
    • MII/RMII/GMII/RGMII Media Independent Interfaces
    • Management Data I/O (MDIO) Module
    • Reset Isolation
    • IEEE 1588 Time-Stamping, AVB, and Industrial Ethernet Protocols
  • Dual USB 2.0 Ports With Integrated PHYs
    • USB2.0 High- and Full-Speed Clients
    • USB2.0 High-, Full-, and Low-Speed Hosts, or OTG
    • Supports End Points 0–15
  • One PCI Express 2.0 Port With Integrated PHY
    • Single Port With One Lane at 5.0 GT/s
    • Configurable as Root Complex or Endpoint
  • Eight 32-Bit General-Purpose Timers (Timer1–8)
  • One System Watchdog Timer (WDT0)
  • Six Configurable UART/IrDA/CIR Modules
    • UART0 With Modem Control Signals
    • Supports up to 3.6864 Mbps UART0/1/2
    • Supports up to 12 Mbps UART3/4/5
    • SIR, MIR, FIR (4.0 MBAUD), and CIR
  • Four Serial Peripheral Interfaces (SPIs) (up to
    48 MHz)
    • Each With Four Chip Selects
  • Three MMC/SD/SDIO Serial Interfaces (up to
    48 MHz)
    • Three Supporting up to 1-, 4-, or 8-Bit Modes
  • Four Inter-Integrated Circuit (I2C Bus) Ports
  • Six Multichannel Audio Serial Ports (McASPs)
    • Dual Ten Serializer Transmit and Receive Ports
    • Quad Four Serializer Transmit and Receive Ports
    • DIT-Capable For S/PDIF (All Ports)
  • Multichannel Buffered Serial Port (McBSP)
    • Transmit and Receive Clocks up to 48 MHz
    • Two Clock Zones and Two Serial Data Pins
    • Supports TDM, I2S, and Similar Formats
  • Real-Time Clock (RTC)
    • One-Time or Periodic Interrupt Generation
  • Up to 128 General-Purpose I/O (GPIO) Pins
  • One Spin Lock Module with up to 128 Hardware Semaphores
  • One Mailbox Module with 12 Mailboxes
  • On-Chip ARM ROM Bootloader (RBL)
  • Power, Reset, and Clock Management
    • Multiple Independent Core Power Domains
    • Multiple Independent Core Voltage Domains
    • Support for Three Operating Points (OPP100, OPP120, OPP166) per Voltage Domain
    • Clock Enable and Disable Control for Subsystems and Peripherals
  • 32KB of Embedded Trace Buffer (ETB) and
    5-Pin Trace Interface for Debug
  • IEEE 1149.1 (JTAG) Compatible
  • 684-Pin Pb-Free BGA Package (CYE Suffix), 0.8-mm Ball Pitch With Via Channel Technology to Reduce PCB Cost
  • 45-nm CMOS Technology

    •  

TMS320DM8127 DaVinci Digital Media processors are highly integrated, programmable platforms that leverage the technology to meet the processing needs of the following applications to name a few:IP Network Cameras Industrial Automation Network Cameras Stereo Cameras Video Surveillance HD Video Conferencing Car Black BoxHome Audio and Video Equipment

The device enables Original-Equipment Manufacturers (OEMs) and Original-Design Manufacturers (ODMs) to quickly bring to market devices featuring robust operating systems support, rich user interfaces, and high processing performance through the maximum flexibility of a fully integrated mixed processor solution. The device also combines programmable video and audio processing with a highly integrated peripheral set.

Programmability is provided by an ARM Cortex-A8 RISC CPU with Neon extension, TI C674x VLIW floating-point DSP core, and high-definition video and imaging coprocessors. The ARM lets developers keep control functions separate from A/V algorithms programmed on the DSP and coprocessors, thus reducing the complexity of the system software. The ARM Cortex-A8 32-Bit RISC Core with Neon floating-point extension includes: 32KB of Instruction cache; 32KB of Data cache; 256KB of L2 Cache; 48KB of Boot ROM; and 64KB of RAM.

The rich peripheral set provides the ability to control external peripheral devices and communicate with external processors. For details on each of the peripherals, see the related sections in this document and the associated peripheral reference guides. The peripheral set includes: HD Video Processing Subsystem Dual Port Gigabit Ethernet MACs (10/100/1000 Mbps) [Ethernet Switch] with MII/RMII/GMII/RGMII and MDIO interface supporting IEEE 1588 Time-Stamping, AVB, and Industrial Ethernet ProtocolsTwo USB ports with integrated 2.0 PHY PCIe x1 GEN2 Compliant interfaceTwo 10-serializer McASP audio serial ports (with DIT mode)Four quad-serilaizer McASP audio serial ports (with DIT mode)One McBSP multichannel buffered serial portSix UARTs with IrDA and CIR supportFour SPI serial interfacesThree MMC/SD/SDIO serial interfacesFour I2C master and slave interfaces Parallel Camera Interface (CAM)Up to 128 General-Purpose I/Os (GPIOs)Eight 32-bit general-purpose timers System watchdog timer Dual DDR2, and DDR3 SDRAM interfacesFlexible 8- or 16-bit asynchronous memory interfaceTwo Controller Area Network (DCAN) modulesSpin LockMailbox

The TMS320DM8127 DaVinci Digital Media processors also include a high-definition video and imaging coprocessor 2 (HDVICP2) to off-load many video and imaging processing tasks from the DSP core, making more DSP MIPS available for common video and imaging algorithms. Additionally, the TMS320DM8127 DaVinci Digital Media processors have a complete set of development tools for both the ARM and DSP which include C compilers, a DSP assembly optimizer to simplify programming and scheduling, and a Microsoft® Windows™ debugger interface for visibility into source code execution.

The C674x DSP core is the high-performance floating-point DSP generation in the TMS320C6000 DSP platform and is code-compatible with previous generation C64x Fixed-Point and C67x Floating-Point DSP generation. The C674x Floating-Point DSP processor uses 32KB of L1 program memory with EDC and 32KB of L1 data memory. Up to 32KB of L1P can be configured as program cache. The remaining memory is noncacheable no-wait-state program memory. Up to 32KB of L1D can be configured as data cache. The remaining memory is noncacheable no-wait-state data memory. The DSP has 256KB of L2 RAM with ECC, which can be defined as SRAM, L2 cache, or a combination of both. All C674x L3 and off-chip

TMS320DM8127 DaVinci Digital Media processors are highly integrated, programmable platforms that leverage the technology to meet the processing needs of the following applications to name a few:IP Network Cameras Industrial Automation Network Cameras Stereo Cameras Video Surveillance HD Video Conferencing Car Black BoxHome Audio and Video Equipment

The device enables Original-Equipment Manufacturers (OEMs) and Original-Design Manufacturers (ODMs) to quickly bring to market devices featuring robust operating systems support, rich user interfaces, and high processing performance through the maximum flexibility of a fully integrated mixed processor solution. The device also combines programmable video and audio processing with a highly integrated peripheral set.

Programmability is provided by an ARM Cortex-A8 RISC CPU with Neon extension, TI C674x VLIW floating-point DSP core, and high-definition video and imaging coprocessors. The ARM lets developers keep control functions separate from A/V algorithms programmed on the DSP and coprocessors, thus reducing the complexity of the system software. The ARM Cortex-A8 32-Bit RISC Core with Neon floating-point extension includes: 32KB of Instruction cache; 32KB of Data cache; 256KB of L2 Cache; 48KB of Boot ROM; and 64KB of RAM.

The rich peripheral set provides the ability to control external peripheral devices and communicate with external processors. For details on each of the peripherals, see the related sections in this document and the associated peripheral reference guides. The peripheral set includes: HD Video Processing Subsystem Dual Port Gigabit Ethernet MACs (10/100/1000 Mbps) [Ethernet Switch] with MII/RMII/GMII/RGMII and MDIO interface supporting IEEE 1588 Time-Stamping, AVB, and Industrial Ethernet ProtocolsTwo USB ports with integrated 2.0 PHY PCIe x1 GEN2 Compliant interfaceTwo 10-serializer McASP audio serial ports (with DIT mode)Four quad-serilaizer McASP audio serial ports (with DIT mode)One McBSP multichannel buffered serial portSix UARTs with IrDA and CIR supportFour SPI serial interfacesThree MMC/SD/SDIO serial interfacesFour I2C master and slave interfaces Parallel Camera Interface (CAM)Up to 128 General-Purpose I/Os (GPIOs)Eight 32-bit general-purpose timers System watchdog timer Dual DDR2, and DDR3 SDRAM interfacesFlexible 8- or 16-bit asynchronous memory interfaceTwo Controller Area Network (DCAN) modulesSpin LockMailbox

The TMS320DM8127 DaVinci Digital Media processors also include a high-definition video and imaging coprocessor 2 (HDVICP2) to off-load many video and imaging processing tasks from the DSP core, making more DSP MIPS available for common video and imaging algorithms. Additionally, the TMS320DM8127 DaVinci Digital Media processors have a complete set of development tools for both the ARM and DSP which include C compilers, a DSP assembly optimizer to simplify programming and scheduling, and a Microsoft® Windows™ debugger interface for visibility into source code execution.

The C674x DSP core is the high-performance floating-point DSP generation in the TMS320C6000 DSP platform and is code-compatible with previous generation C64x Fixed-Point and C67x Floating-Point DSP generation. The C674x Floating-Point DSP processor uses 32KB of L1 program memory with EDC and 32KB of L1 data memory. Up to 32KB of L1P can be configured as program cache. The remaining memory is noncacheable no-wait-state program memory. Up to 32KB of L1D can be configured as data cache. The remaining memory is noncacheable no-wait-state data memory. The DSP has 256KB of L2 RAM with ECC, which can be defined as SRAM, L2 cache, or a combination of both. All C674x L3 and off-chip
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모두 보기18
유형 직함 날짜
* Data sheet TMS320DM8127 DaVinci™ Video Processors datasheet (Rev. C) 2014/03/25
* Errata TMS320DM8127 DaVinci™ Video Processors Errata (Silicon Revs 3.0, 2.1) (Rev. C) 2014/03/25
* User guide TMS320DM8127 and TMS320DM814x DaVinci™ Digital Media Processors TRM (Rev. G) 2016/06/30
Application note High-Speed Interface Layout Guidelines (Rev. J) PDF | HTML 2023/02/24
More literature TMDSCSK8127 Quick Start Guide 2017/01/05
White paper Low-latency design considerations for video-enabled aerial drones 2016/09/15
User guide DM38x and TMS320DM8127 DaVinci™ Face Detect User's Guide (Rev. A) 2016/06/30
User guide DM38x and TMS320DM8127 DaVinci™ Imaging Subsystem (ISS) User's Guide (Rev. A) 2016/06/30
Application note Error Detection and Correction Mechanism of TMS320C64x+/C674x (Rev. A) 2013/07/19
More literature DM81x Design Network Partners 2012/06/05
Application note TI814x-DDR3-Init-U-Boot 2011/10/31
Application note Introduction to TMS320C6000 DSP Optimization 2011/10/06
Product overview DaVinci DM8168 and DM8148 Product Bulletin 2011/03/01
Product overview Software Makes Development Easy for DM8168 and DM8148 2011/03/01
Product overview Video Analytics on TI's Davinci Digital Media Processors Backgrounder 2011/03/01
White paper C6Accel Whitepaper 2010/09/22
User guide TMS320C674x DSP CPU and Instruction Set User's Guide (Rev. B) 2010/07/30
Application note Canny Edge Detection Implementation on TMS320C64x/64x+ Using VLIB 2009/11/25

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Z3-3P-VIDEO-EVMS — Z3 기술 프로세서 비디오 평가 모듈

Z3 develops and supports open-source software architectures focused on TI's DaVinci and AM57x processors. Products include multimedia centric framework, peripheral drivers, production modules and complete product design services. Z3 also provides system level design and integration for both wired (...)
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TMDSEMU200-U — XDS200 USB 디버그 프로브

XDS200은 TI 임베디드 디바이스 디버깅에 사용되는 디버그 프로브(에뮬레이터)입니다. XDS200은 저렴한 XDS110 및 고성능 XDS560v2에 비해 저렴한 비용으로 우수한 성능을 균형 있게 제공합니다. 단일 포드에서 광범위한 표준(IEEE1149.1, IEEE1149.7, SWD)을 지원합니다. 모든 XDS 디버그 프로브는 ETB(Embedded Trace Buffer)를 특징으로 하는 모든 Arm® 및 DSP 프로세서에서 코어 및 시스템 추적을 지원합니다. 핀을 통한 코어 추적의 경우 XDS560v2 PRO TRACE가 (...)

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디버그 프로브

TMDSEMU560V2STM-U — XDS560v2 시스템 추적 USB 디버그 프로브

XDS560v2는 디버그 프로브의 XDS560™ 제품군 중 최고의 성능을 가진 제품으로, 기존의 JTAG 표준(IEEE1149.1)과 cJTAG(IEEE1149.7)를 모두 지원합니다. SWD(직렬 와이어 디버그)는 지원하지 않습니다.

모든 XDS 디버그 프로브는 ETB(Embedded Trace Buffer)를 특징으로 하는 모든 ARM 및 DSP 프로세서에서 코어 및 시스템 추적을 지원합니다. 핀을 통한 추적의 경우 XDS560v2 PRO TRACE가 필요합니다.

XDS560v2는 MIPI HSPT 60핀 커넥터(TI 14핀, (...)

TI.com에서 구매할 수 없습니다
디버그 프로브

TMDSEMU560V2STM-UE — XDS560v2 시스템 추적 USB 및 이더넷 디버그 프로브

The XDS560v2 is the highest performance of the XDS family of debug probes and supports both the traditional JTAG standard (IEEE1149.1) and cJTAG (IEEE1149.7). Note that it does not support serial wire debug (SWD).

All XDS debug probes support Core and System Trace in all ARM and DSP processors that (...)

TI.com에서 구매할 수 없습니다
소프트웨어 개발 키트(SDK)

LINUXEZSDK-DAVINCI — Linux EZ Software Development Kit (EZSDK) for DM814x and DM816x - ALPHA

The Linux EZ Software Development Kit (EZ SDK) allows customers to evaluate their devices in minutes and begin development in less than an hour. This kit provides everything DaVinci™ developers need to evaluate and start developing on the DaVinci™ DM816x/DM814x processors. With the (...)

지원되는 제품 및 하드웨어

지원되는 제품 및 하드웨어

제품
Arm 기반 프로세서
TMS320DM8127 — DaVinci 디지털 미디어 프로세서 TMS320DM8147 — DaVinci 디지털 미디어 프로세서 TMS320DM8148 — DaVinci 디지털 미디어 프로세서
DSP(디지털 신호 프로세서)
TMS320DM8165 — DaVinci 디지털 미디어 프로세서 TMS320DM8167 — DaVinci 디지털 미디어 프로세서 TMS320DM8168 — DaVinci 디지털 미디어 프로세서
다운로드 옵션
드라이버 또는 라이브러리

C64X-DSPLIB — Download TMS320C64x DSP Library

TMS320C6000 Digital Signal Processor Library (DSPLIB) is a platform-optimized DSP function library for C programmers. It includes C-callable, general-purpose signal-processing routines that are typically used in computationally intensive real-time applications. With these routines, higher (...)

지원되는 제품 및 하드웨어

지원되는 제품 및 하드웨어

제품
Arm 기반 프로세서
OMAPL137-HT — 고온 저전력 C674x 부동 소수점 DSP + Arm 프로세서 - 최대 456MHz OMAPL138B-EP — 향상된 제품 저전력 C674x 부동 소수점 DSP + Arm9 프로세서 - 345MHz TMS320DM8127 — DaVinci 디지털 미디어 프로세서
DSP(디지털 신호 프로세서)
SM320C6201-EP — 향상된 제품 C6201 고정 소수점 DSP SM320C6415 — 군사용 등급 C64x 고정 소수점 DSP SM320C6415-EP — 향상된 제품 C6415 고정 소수점 DSP SM320C6424-EP — EP(Enhanced Product) C6424 고정 소수점 DSP SM320C6455-EP — EP(Enhanced Product) C6455 고정 소수점 DSP SM320C6472-HIREL — 높은 안정성 제품 6 코어 C6472 고정 소수점 DSP SM320C6678-HIREL — 고신뢰성 제품 고성능 8코어 C6678 고정 및 부동 소수점 DSP SM320C6701 — 군사용 애플리케이션을 위한 단일 코어 C67x 부동 소수점 DSP - 최대 167MHz SM320C6701-EP — 향상된 제품 C6701 부동 소수점 DSP SM320C6711D-EP — 향상된 제품 C6711D 부동 소수점 DSP SM320C6712D-EP — 향상된 제품 C6712D DSP SM320C6713B-EP — 향상된 제품 C6713 부동 소수점 DSP SM320C6727B — 군사용 등급 C6727B 부동 소수점 DSP SM320C6727B-EP — 향상된 제품 C6727 부동 소수점 DSP SM320DM642-HIREL — 높은 안정성 제품 디지털 미디어 DM642 DSP SM32C6416T-EP — 향상된 제품 C6416T 고정 소수점 DSP SMJ320C6201B — 고정 소수점 디지털 신호 프로세서, 군사용 SMJ320C6203 — 군사용 등급 C62x 고정 소수점 DSP - 세라믹 패키지 SMJ320C6415 — 군사용 등급 C64x 고정 소수점 DSP - 세라믹 패키지 SMJ320C6701 — 군사용 등급 C67x 부동 소수점 DSP - 세라믹 패키지 SMJ320C6701-SP — 우주 항공 등급 C6701 부동 소수점 DSP - 세라믹 패키지를 지원하는 방사능 내성 클래스 V SMV320C6727B-SP — 우주 항공 등급 C6727B 부동 소수점 DSP - 세라믹 패키지를 지원하는 방사능 내성 클래스 V TMS320C6201 — 고정소수점 디지털 신호 프로세서 TMS320C6202 — 고정소수점 디지털 신호 프로세서 TMS320C6202B — C62x 고정 소수점 DSP - 최대 300MHz, 384KB TMS320C6203B — C62x 고정 소수점 DSP - 최대 300MHz, 896KB TMS320C6204 — 고정소수점 디지털 신호 프로세서 TMS320C6205 — 고정소수점 디지털 신호 프로세서 TMS320C6211B — C62x 고정 소수점 DSP - 최대 167MHz TMS320C6421Q — C64x+ 고정 소수점 DSP - 최대 600MHz, 8비트 EMIFA, 16비트 DDR2 TMS320C6424Q — C64x+ 고정 소수점 DSP - 최대 600MHz, 16/8비트 EMIFA, 32/16비트 DDR2 TMS320C6452 — C64x+ 고정 소수점 DSP - 최대 900MHz, 1Gbps 이더넷 TMS320C6454 — C64x+ 고정 소수점 DSP - 최대 1GHz, 64비트 EMIFA, 32/16비트 DDR2, 1Gbps 이더넷 TMS320C6455 — C64x+ 고정 소수점 DSP - 최대 1.2GHz, 64비트 EMIFA, 32/16비트 DDR2, 1Gbps 이더넷 TMS320C6457 — 통신 인프라 디지털 신호 프로세서 TMS320C6701 — C67x 부동 소수점 DSP - 최대 167MHz, McBSP TMS320C6711D — C67x 부동 소수점 DSP - 최대 250MHz, McBSP, 32비트 EMIFA TMS320C6712D — C67x 부동 소수점 DSP - 최대 150MHz, McBSP, 16비트 EMIFA TMS320C6720 — C67x 부동 소수점 DSP - 200MHz, McASP, 16비트 EMIFA TMS320C6722B — C67x 부동 소수점 DSP - 최대 250MHz, McASP, 16비트 EMIFA TMS320C6726B — C67x 부동 소수점 DSP - 최대 266MHz, McASP, 16비트 EMIFA TMS320C6727 — C67x 부동 소수점 DSP - 최대 250MHz, McASP, 32비트 EMIFA TMS320C6727B — C67x 부동 소수점 DSP - 최대 350MHz, McASP, 32비트 EMIFA TMS320C6743 — 저전력 C674x 부동 소수점 DSP - 375MHz TMS320C6745 — 저전력 C674x 부동 소수점 DSP - 456MHz, QFP TMS320C6747 — 저전력 C674x 부동 소수점 DSP - 456MHz, PBGA
다운로드
드라이버 또는 라이브러리

C67X-DSPLIB — Download TMS320C67x DSP Library

TMS320C6000 Digital Signal Processor Library (DSPLIB) is a platform-optimized DSP function library for C programmers. It includes C-callable, general-purpose signal-processing routines that are typically used in computationally intensive real-time applications. With these routines, higher (...)

지원되는 제품 및 하드웨어

지원되는 제품 및 하드웨어

제품
Arm 기반 프로세서
OMAPL137-HT — 고온 저전력 C674x 부동 소수점 DSP + Arm 프로세서 - 최대 456MHz OMAPL138B-EP — 향상된 제품 저전력 C674x 부동 소수점 DSP + Arm9 프로세서 - 345MHz TMS320DM8127 — DaVinci 디지털 미디어 프로세서
DSP(디지털 신호 프로세서)
SM320C6201-EP — 향상된 제품 C6201 고정 소수점 DSP SM320C6415 — 군사용 등급 C64x 고정 소수점 DSP SM320C6415-EP — 향상된 제품 C6415 고정 소수점 DSP SM320C6424-EP — EP(Enhanced Product) C6424 고정 소수점 DSP SM320C6455-EP — EP(Enhanced Product) C6455 고정 소수점 DSP SM320C6472-HIREL — 높은 안정성 제품 6 코어 C6472 고정 소수점 DSP SM320C6678-HIREL — 고신뢰성 제품 고성능 8코어 C6678 고정 및 부동 소수점 DSP SM320C6701 — 군사용 애플리케이션을 위한 단일 코어 C67x 부동 소수점 DSP - 최대 167MHz SM320C6701-EP — 향상된 제품 C6701 부동 소수점 DSP SM320C6711D-EP — 향상된 제품 C6711D 부동 소수점 DSP SM320C6712D-EP — 향상된 제품 C6712D DSP SM320C6713B-EP — 향상된 제품 C6713 부동 소수점 DSP SM320C6727B — 군사용 등급 C6727B 부동 소수점 DSP SM320C6727B-EP — 향상된 제품 C6727 부동 소수점 DSP SM320DM642-HIREL — 높은 안정성 제품 디지털 미디어 DM642 DSP SM32C6416T-EP — 향상된 제품 C6416T 고정 소수점 DSP SMJ320C6201B — 고정 소수점 디지털 신호 프로세서, 군사용 SMJ320C6203 — 군사용 등급 C62x 고정 소수점 DSP - 세라믹 패키지 SMJ320C6415 — 군사용 등급 C64x 고정 소수점 DSP - 세라믹 패키지 SMJ320C6701 — 군사용 등급 C67x 부동 소수점 DSP - 세라믹 패키지 SMJ320C6701-SP — 우주 항공 등급 C6701 부동 소수점 DSP - 세라믹 패키지를 지원하는 방사능 내성 클래스 V SMV320C6727B-SP — 우주 항공 등급 C6727B 부동 소수점 DSP - 세라믹 패키지를 지원하는 방사능 내성 클래스 V TMS320C6201 — 고정소수점 디지털 신호 프로세서 TMS320C6202 — 고정소수점 디지털 신호 프로세서 TMS320C6202B — C62x 고정 소수점 DSP - 최대 300MHz, 384KB TMS320C6203B — C62x 고정 소수점 DSP - 최대 300MHz, 896KB TMS320C6204 — 고정소수점 디지털 신호 프로세서 TMS320C6205 — 고정소수점 디지털 신호 프로세서 TMS320C6211B — C62x 고정 소수점 DSP - 최대 167MHz TMS320C6421Q — C64x+ 고정 소수점 DSP - 최대 600MHz, 8비트 EMIFA, 16비트 DDR2 TMS320C6424Q — C64x+ 고정 소수점 DSP - 최대 600MHz, 16/8비트 EMIFA, 32/16비트 DDR2 TMS320C6452 — C64x+ 고정 소수점 DSP - 최대 900MHz, 1Gbps 이더넷 TMS320C6454 — C64x+ 고정 소수점 DSP - 최대 1GHz, 64비트 EMIFA, 32/16비트 DDR2, 1Gbps 이더넷 TMS320C6455 — C64x+ 고정 소수점 DSP - 최대 1.2GHz, 64비트 EMIFA, 32/16비트 DDR2, 1Gbps 이더넷 TMS320C6457 — 통신 인프라 디지털 신호 프로세서 TMS320C6701 — C67x 부동 소수점 DSP - 최대 167MHz, McBSP TMS320C6711D — C67x 부동 소수점 DSP - 최대 250MHz, McBSP, 32비트 EMIFA TMS320C6712D — C67x 부동 소수점 DSP - 최대 150MHz, McBSP, 16비트 EMIFA TMS320C6720 — C67x 부동 소수점 DSP - 200MHz, McASP, 16비트 EMIFA TMS320C6722B — C67x 부동 소수점 DSP - 최대 250MHz, McASP, 16비트 EMIFA TMS320C6726B — C67x 부동 소수점 DSP - 최대 266MHz, McASP, 16비트 EMIFA TMS320C6727 — C67x 부동 소수점 DSP - 최대 250MHz, McASP, 32비트 EMIFA TMS320C6727B — C67x 부동 소수점 DSP - 최대 350MHz, McASP, 32비트 EMIFA TMS320C6743 — 저전력 C674x 부동 소수점 DSP - 375MHz TMS320C6745 — 저전력 C674x 부동 소수점 DSP - 456MHz, QFP TMS320C6747 — 저전력 C674x 부동 소수점 DSP - 456MHz, PBGA
다운로드
드라이버 또는 라이브러리

SPRC264 — TMS320C5000/6000 이미지 라이브러리(IMGLIB)

C5000/6000 Image Processing Library (IMGLIB) is an optimized image/video processing function library for C programmers. It includes C-callable general-purpose image/video processing routines that are typically used in computationally intensive real-time applications. With these routines, higher (...)
사용 설명서: PDF
옵션 보기
IDE, 구성, 컴파일러 또는 디버거

CCSTUDIO — Code Composer Studio integrated development environment (IDE)

Code Composer Studio is an integrated development environment (IDE) for TI's microcontrollers and processors. It comprises a suite of tools used to develop and debug embedded applications.  Code Composer Studio is available for download across Windows®, Linux® and macOS® (...)

지원되는 제품 및 하드웨어

지원되는 제품 및 하드웨어

이 설계 리소스는 이러한 범주의 제품 대부분을 지원합니다.

제품 세부 정보 페이지에서 지원을 확인하십시오.
시작 다운로드 옵션
시뮬레이션 모델

DM814x, DM8127 CYE BSDL Model (Rev. A)

SPRM550A.ZIP (16 KB) - BSDL Model
다운로드
시뮬레이션 모델

DM814x, DM8127 CYE IBIS Model, Revision 2.01 (Rev. A)

SPRM555A.ZIP (3890 KB) - IBIS Model
다운로드
설계 툴

PROCESSORS-3P-SEARCH — Arm 기반 MPU, arm 기반 MCU 및 DSP 타사 검색 툴

TI는 여러 회사와의 협력을 통해 TI 프로세서를 사용하여 광범위한 소프트웨어, 툴 및 SOM을 제공해서 생산 단계로 가는 속도를 높이고 있습니다. 이 검색 툴을 다운로드하여 타사 솔루션을 빠르게 검색하고 필요에 맞는 올바른 타사를 찾아보세요. 여기에 나열된 소프트웨어, 툴 및 모듈은 텍사스 인스트루먼트가 아닌 독립적인 타사에서 생산 및 관리하고 있습니다.

검색 툴은 다음과 같이 제품 유형별로 분류되어 있습니다.

  • 툴에는 IDE/컴파일러, 디버그 및 추적, 시뮬레이션 및 모델링 소프트웨어, 플래시 프로그래머가 포함되어 있습니다.
  • OS에는 (...)
다운로드
패키지 핀 다운로드
FCBGA (CYE) 684 옵션 보기
TI의 평가 항목에 대한 표준 약관이 적용됩니다.

주문 및 품질

포함된 정보:
  • RoHS
  • REACH
  • 디바이스 마킹
  • 납 마감/볼 재질
  • MSL 등급/피크 리플로우
  • MTBF/FIT 예측
  • 물질 성분
  • 인증 요약
  • 지속적인 신뢰성 모니터링
포함된 정보:
  • 팹 위치
  • 조립 위치

권장 제품에는 본 TI 제품과 관련된 매개 변수, 평가 모듈 또는 레퍼런스 디자인이 있을 수 있습니다.

지원 및 교육

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포럼 주제 모두 보기(영문)

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