TPS51200-EP
- Input Voltage: Supports 2.5-V Rail and 3.3-V Rail
- VLDOIN Voltage Range: 1.1 V to 3.5 V
- Sink and Source Termination Regulator Includes
Droop Compensation - Requires Minimum Output Capacitance of 20-µF
(Typically 3 × 10-µF MLCCs) for Memory
Termination Applications (DDR) - PGOOD to Monitor Output Regulation
- EN Input
- REFIN Input Allows for Flexible Input Tracking
Either Directly or Through Resistor Divider - Remote Sensing (VOSNS)
- ±10-mA Buffered Reference (REFOUT)
- Built-in Soft Start, UVLO, and OCL
- Thermal Shutdown
- Meets DDR and DDR2 JEDEC Specifications
- Supports DDR3, Low-Power DDR3, and DDR4
VTT Applications - 10-Pin VSON Package With Thermal Pad
- Supports Defense, Aerospace, and Medical
Applications- Controlled Baseline
- One Assembly and Test Site
- One Fabrication Site
- Available in Military (–55°C to 125°C)
Temperature Range - Extended Product Life Cycle
- Extended Product-Change Notification
- Product Traceability
The TPS51200-EP device is a sink and source double data rate (DDR) termination regulator specifically designed for low-input voltage, low-cost, low-noise systems where space is a key consideration.
The TPS51200-EP maintains a fast transient response and only requires a minimum output capacitance of 20 µF. The TPS51200-EP supports a remote sensing function and all power requirements for DDR, DDR2, DDR3, Low-Power DDR3, and DDR4 VTT bus termination.
In addition, the TPS51200-EP provides an open-drain PGOOD signal to monitor the output regulation and an EN signal that can be used to discharge VTT during S3 (suspend to RAM) for DDR applications.
The TPS51200-EP is available in the thermally efficient 10-pin VSON thermal pad package, and is rated both Green and Pb-free. It is specified from –55°C to +125°C.
기술 문서
| 유형 | 직함 | 날짜 | ||
|---|---|---|---|---|
| * | Data sheet | TPS51200-EP Sink and Source DDR Termination Regulator datasheet | PDF | HTML | 2016/06/29 |
| * | VID | TPS51200-EP VID V6216610 | 2018/03/27 | |
| * | Radiation & reliability report | TPS51200MDRCTEP Reliability Report | 2016/09/21 |
설계 및 개발
추가 조건 또는 필수 리소스는 사용 가능한 경우 아래 제목을 클릭하여 세부 정보 페이지를 확인하세요.
TPS51200EVM — TPS51200 싱크 소스 DDR 터미네이션 레귤레이터
TPS51200EVM 평가 보드인 HPA322A는 TI의 비용에 최적화된 DDR/DDR2/DDR3/LP DDR3 VTT 터미네이션 레귤레이터인 TPS51200의 성능과 특성을 평가하도록 설계되었습니다. TPS51200은 최소한의 외부 부품으로 DDR(2.5V/1.25V), DDR2(1.8V/0.9V), DDR3(1.5V/0.75V), LP DDR3(1.2V/0.6V) 사양을 지원하는 DDR 메모리에 적절한 터미네이션 전압 및 10mA 버퍼 레퍼런스 전압을 제공하도록 설계되었습니다.
TPS51200 TINA-TI Start-Up Transient Reference Design
| 패키지 | 핀 | 다운로드 |
|---|---|---|
| VSON (DRC) | 10 | 옵션 보기 |
주문 및 품질
- RoHS
- REACH
- 디바이스 마킹
- 납 마감/볼 재질
- MSL 등급/피크 리플로우
- MTBF/FIT 예측
- 물질 성분
- 인증 요약
- 지속적인 신뢰성 모니터링
- 팹 위치
- 조립 위치
권장 제품에는 본 TI 제품과 관련된 매개 변수, 평가 모듈 또는 레퍼런스 디자인이 있을 수 있습니다.