Home Amplifiers Programmable & variable gain amplifiers (PGAs & VGAs)
Home
Amplifiers
Programmable & variable gain amplifiers (PGAs & VGAs)

PGA113

ACTIVE

Zero-drift, 100-µV offset, 12-nV/√Hz noise, RRO (scope gain) programmable gain amp with 2-ch mux

Order now
Data sheet

PGA113

ACTIVE
Data sheet Order now

Product details

PGA/VGA PGA Number of channels 2 Vs (min) (V) 2.2 Vs (max) (V) 5.5 Input type Single-ended Output type Single-ended Input offset drift (±) (typ) (µV/°C) 0.6 Interface type SPI Noise at 1 kHz (typ) (V√Hz) 0.000000013 BW at Acl (MHz) 10 Acl, min spec gain (V/V) 1 Gain (max) (dB) 46 Architecture CMOS Features Binary gains, Daisy chain, Shutdown Vos (offset voltage at 25°C) (typ) (mV) 0.025 Input voltage noise (typ) (µV√Hz) 0.012 Slew rate (typ) (V/µs) 3 Iq per channel (typ) (mA) 1.08 Gain error (typ) (%) 0.006 Gain drift (max) (ppm/°C) 0.5 Rating Catalog Operating temperature range (°C) -40 to 125
PGA/VGA PGA Number of channels 2 Vs (min) (V) 2.2 Vs (max) (V) 5.5 Input type Single-ended Output type Single-ended Input offset drift (±) (typ) (µV/°C) 0.6 Interface type SPI Noise at 1 kHz (typ) (V√Hz) 0.000000013 BW at Acl (MHz) 10 Acl, min spec gain (V/V) 1 Gain (max) (dB) 46 Architecture CMOS Features Binary gains, Daisy chain, Shutdown Vos (offset voltage at 25°C) (typ) (mV) 0.025 Input voltage noise (typ) (µV√Hz) 0.012 Slew rate (typ) (V/µs) 3 Iq per channel (typ) (mA) 1.08 Gain error (typ) (%) 0.006 Gain drift (max) (ppm/°C) 0.5 Rating Catalog Operating temperature range (°C) -40 to 125
VSSOP (DGS) 10 14.7 mm² (3 mm × 4.9 mm)
  • Rail-to-Rail Input and Output
  • Offset: 25 µV (Typical), 100 µV
    (Maximum)
  • Zerø Drift: 0.35 µV/°C (Typical), 1.2 µV/°C
    (Maximum)
  • Low Noise: 12 nV/√Hz
  • Input Offset Current: ±5 nA Maximum (25°C)
  • Gain Error: 0.1% Maximum (G ≥ 32),
    0.3% Maximum (G > 32)
  • Binary Gains: 1, 2, 4, 8, 16, 32, 64, 128 (PGA112,
    PGA116)
  • Scope Gains: 1, 2, 5, 10, 20, 50, 100, 200
    (PGA113, PGA117)
  • Gain Switching Time: 200 ns
  • 2 Channel MUX: PGA112, PGA113
    10 Channel MUX: PGA116, PGA117
  • Four Internal Calibration Channels
  • Amplifier Optimized for Driving CDAC ADCs
  • Output Swing: 50 mV to Supply Rails
  • AVDD and DVDD for Mixed Voltage Systems
  • IQ = 1.1 mA (Typical)
  • Software and Hardware Shutdown: IQ ≤ 4 µA
    (Typical)
  • Temperature Range: –40°C to 125°C
  • SPI™ Interface (10 MHz) With Daisy-Chain
    Capability
  • Rail-to-Rail Input and Output
  • Offset: 25 µV (Typical), 100 µV
    (Maximum)
  • Zerø Drift: 0.35 µV/°C (Typical), 1.2 µV/°C
    (Maximum)
  • Low Noise: 12 nV/√Hz
  • Input Offset Current: ±5 nA Maximum (25°C)
  • Gain Error: 0.1% Maximum (G ≥ 32),
    0.3% Maximum (G > 32)
  • Binary Gains: 1, 2, 4, 8, 16, 32, 64, 128 (PGA112,
    PGA116)
  • Scope Gains: 1, 2, 5, 10, 20, 50, 100, 200
    (PGA113, PGA117)
  • Gain Switching Time: 200 ns
  • 2 Channel MUX: PGA112, PGA113
    10 Channel MUX: PGA116, PGA117
  • Four Internal Calibration Channels
  • Amplifier Optimized for Driving CDAC ADCs
  • Output Swing: 50 mV to Supply Rails
  • AVDD and DVDD for Mixed Voltage Systems
  • IQ = 1.1 mA (Typical)
  • Software and Hardware Shutdown: IQ ≤ 4 µA
    (Typical)
  • Temperature Range: –40°C to 125°C
  • SPI™ Interface (10 MHz) With Daisy-Chain
    Capability

The PGA112 and PGA113 devices (binary and scope gains) offer two analog inputs, a three-pin SPI interface, and software shutdown in a 10-pin, VSSOP package. The PGA116 and PGA117 (binary and scope gains) offer 10 analog inputs, a SPI interface with daisy-chain capability, and hardware and software shutdown in a 20-pin TSSOP package.

All versions provide internal calibration channels for system-level calibration. The channels are tied to GND, 0.9 VCAL, 0.1 VCAL, and VREF, respectively. VCAL, an external voltage connected to Channel 0, is used as the system calibration reference. Binary gains are: 1, 2, 4, 8, 16, 32, 64, and 128; scope gains are: 1, 2, 5, 10, 20, 50, 100, and 200.

The PGA112 and PGA113 devices (binary and scope gains) offer two analog inputs, a three-pin SPI interface, and software shutdown in a 10-pin, VSSOP package. The PGA116 and PGA117 (binary and scope gains) offer 10 analog inputs, a SPI interface with daisy-chain capability, and hardware and software shutdown in a 20-pin TSSOP package.

All versions provide internal calibration channels for system-level calibration. The channels are tied to GND, 0.9 VCAL, 0.1 VCAL, and VREF, respectively. VCAL, an external voltage connected to Channel 0, is used as the system calibration reference. Binary gains are: 1, 2, 4, 8, 16, 32, 64, and 128; scope gains are: 1, 2, 5, 10, 20, 50, 100, and 200.
filter Find other Programmable & variable gain amplifiers (PGAs & VGAs)
Download View video with transcript Video

Similar products you might be interested in

open-in-new Compare alternates
Pin-for-pin with same functionality to the compared device.
PGA112 ACTIVE Zero-drift, 100-µV offset, 12-nV/√Hz noise, RRO (binary gain) programmable gain amp with 2-ch mux This device offers binary gains 1, 2, 4, 8, 16, 32, 64, 128 instead of scope gains
Same functionality with different pin-out to the compared device.
PGA116 ACTIVE Zero-Drift, 100-µV offset, 12-nV/√Hz noise, RRO (binary gain) programmable gain amp w This device offers 10 channel mux instead of 2 channel mux, and binary gains instead of scope gains.
PGA117 ACTIVE Zero-drift, 100-µV offset, 12-nV/√Hz noise, RRO (scope gain) programmable gain amp with 10-ch mux This device offers 10 channel mux instead of 2 channel mux.
LMP8358 ACTIVE Zero-Drift, Programmable Instrumentation Amplifier with Diagnostics Dual-channel scope gains with SPI Interface

Technical documentation

No results found. Please clear your search and try again.
View all 1
Top documentation Type Title Format options Date
* Data sheet PGA11x Zerø-Drift Programmable Gain Amplifier With Mux datasheet (Rev. C) PDF | HTML Nov 30, 2015

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Evaluation board

PGA113EVM-B — PGA113 Evaluation Module Rev B

The PGA113EVM is an evaluation module that is used to fully evaluate the PGA113 programmable gain amplifier. The PGA113EVM consists of two printed circuit boards (PCBs). One board (the SM-USB-DIG Platform) generates the digital signals required to communicate with the PGA113. The second board is (...)

User guide: PDF
Supported products & hardware
In stock
Limit:
??asset.out-of-stock-ti_en_US??
Not available
Support software

SBOC272 — PGA112/113EVM Software

Supported products & hardware
Support software

SBOC426 — PGA112/113EVM Source Code

Supported products & hardware
Package Pins CAD symbols, footprints & 3D models
VSSOP (DGS) 10 Ultra Librarian
TI's Standard Terms and Conditions for Evaluation Items apply.

Ordering & quality

Support & training

TI E2E™ forums with technical support from TI engineers

View all forum topics

Content is provided "as is" by TI and community contributors and does not constitute TI specifications. See terms of use.

If you have questions about quality, packaging or ordering TI products, see TI support. ​​​​​​​​​​​​​​

Videos