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Direction-controlled voltage translators

SN74LVC16T245-EP

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Enhanced Product 16-Bit Dual-Supply Bus Transceiver

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Data sheet

SN74LVC16T245-EP

ACTIVE
Data sheet Order now

Product details

Technology family LVC Applications GPIO Bits (#) 16 High input voltage (min) (V) 1.08 High input voltage (max) (V) 5.5 Vout (min) (V) 1.65 Vout (max) (V) 5.5 Data rate (max) (Mbps) 200 IOH (max) (mA) -32 IOL (max) (mA) 32 Supply current (max) (µA) 30 Features Output enable, Overvoltage tolerant inputs, Partial power down (Ioff) Input type Standard CMOS Output type 3-State, Balanced CMOS, Push-Pull Rating HiRel Enhanced Product Operating temperature range (°C) -55 to 125
Technology family LVC Applications GPIO Bits (#) 16 High input voltage (min) (V) 1.08 High input voltage (max) (V) 5.5 Vout (min) (V) 1.65 Vout (max) (V) 5.5 Data rate (max) (Mbps) 200 IOH (max) (mA) -32 IOL (max) (mA) 32 Supply current (max) (µA) 30 Features Output enable, Overvoltage tolerant inputs, Partial power down (Ioff) Input type Standard CMOS Output type 3-State, Balanced CMOS, Push-Pull Rating HiRel Enhanced Product Operating temperature range (°C) -55 to 125
TSSOP (DGG) 48 101.25 mm² 12.5 x 8.1
  • Control Inputs VIH and VIL Levels Are
    Referenced to VCCA Voltage
  • VCC Isolation Feature – If Either VCC
    Input Is at GND, Both Ports Are in the High-Impedance State
  • Overvoltage-Tolerant Inputs and Outputs Allow Mixed-Voltage-Mode Data
    Communications
  • Fully Configurable Dual-Rail Design Allows Each Port to Operate Over the Full
    1.65-V to 5.5-V Power-Supply Range
  • Ioff Supports Partial-Power-Down Mode Operation
  • Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)
    • 1000-V Charged-Device Model (C101)
  • Control Inputs VIH and VIL Levels Are
    Referenced to VCCA Voltage
  • VCC Isolation Feature – If Either VCC
    Input Is at GND, Both Ports Are in the High-Impedance State
  • Overvoltage-Tolerant Inputs and Outputs Allow Mixed-Voltage-Mode Data
    Communications
  • Fully Configurable Dual-Rail Design Allows Each Port to Operate Over the Full
    1.65-V to 5.5-V Power-Supply Range
  • Ioff Supports Partial-Power-Down Mode Operation
  • Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)
    • 1000-V Charged-Device Model (C101)

This 16-bit noninverting bus transceiver uses two separate configurable power-supply rails. The A port is designed to track VCCA. VCCA accepts any supply voltage from 1.65 V to 5.5 V. The B port is designed to track VCCB. VCCB accepts any supply voltage from 1.65 V to 5.5 V. This allows for universal low-voltage bidirectional translation between any of the 1.8-V, 2.5-V, 3.3-V, and 5-V voltage nodes.

The SN74LVC16T245 is designed for asynchronous communication between two data buses. The logic levels of the direction-control (DIR) input and the output-enable (OE) input activate either the B-port outputs or the A-port outputs or place both output ports into the high-impedance mode. The device transmits data from the A bus to the B bus when the B-port outputs are activated, and from the B bus to the A bus when the A-port outputs are activated. The input circuitry on both A and B ports always is active and must have a logic HIGH or LOW level applied to prevent excess ICC and ICCZ.

The SN74LVC16T245 is designed so that the control pins (1DIR, 2DIR, 1OE, and 2OE) are supplied by VCCA.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

The VCC isolation feature ensures that if either VCC input is at GND, then both ports are in the high-impedance state.

To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

This 16-bit noninverting bus transceiver uses two separate configurable power-supply rails. The A port is designed to track VCCA. VCCA accepts any supply voltage from 1.65 V to 5.5 V. The B port is designed to track VCCB. VCCB accepts any supply voltage from 1.65 V to 5.5 V. This allows for universal low-voltage bidirectional translation between any of the 1.8-V, 2.5-V, 3.3-V, and 5-V voltage nodes.

The SN74LVC16T245 is designed for asynchronous communication between two data buses. The logic levels of the direction-control (DIR) input and the output-enable (OE) input activate either the B-port outputs or the A-port outputs or place both output ports into the high-impedance mode. The device transmits data from the A bus to the B bus when the B-port outputs are activated, and from the B bus to the A bus when the A-port outputs are activated. The input circuitry on both A and B ports always is active and must have a logic HIGH or LOW level applied to prevent excess ICC and ICCZ.

The SN74LVC16T245 is designed so that the control pins (1DIR, 2DIR, 1OE, and 2OE) are supplied by VCCA.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

The VCC isolation feature ensures that if either VCC input is at GND, then both ports are in the high-impedance state.

To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
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Technical documentation

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Type Title Date
* Data sheet SN74LVC16T245-EP 16-BIT DUAL-SUPPLY BUS TRANSCEIVER datasheet (Rev. A) 12 Feb 2013
* VID SN74LVC16T245-EP VID V6212667 21 Jun 2016
* Radiation & reliability report CLVC16T245MDGGREP Reliability Report 24 Apr 2013
* Radiation & reliability report CLVC16T245MDGGREP Reliability Report 24 Apr 2013
Application note Implications of Slow or Floating CMOS Inputs (Rev. E) 26 Jul 2021
Application brief Voltage Translation for Rugged High Reliability Applications PDF | HTML 20 Jul 2021
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Product overview Design Summary for WCSP Little Logic (Rev. B) 04 Nov 2004
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 08 Jul 2004
Application note Selecting the Right Level Translation Solution (Rev. A) 22 Jun 2004
User guide Signal Switch Data Book (Rev. A) 14 Nov 2003
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User guide LVC and LV Low-Voltage CMOS Logic Data Book (Rev. B) 18 Dec 2002
Application note Texas Instruments Little Logic Application Report 01 Nov 2002
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Application note 16-Bit Widebus Logic Families in 56-Ball, 0.65-mm Pitch Very Thin Fine-Pitch BGA (Rev. B) 22 May 2002
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