ADC12DJ4000RF
- ADC core:
- 12-bit resolution
- Up to 8GSPS in single-channel mode
- Up to 4GSPS in dual-channel mode
- Performance specifications:
- Noise floor (–20dBFS, VFS =
1VPP-DIFF):
- Dual-channel mode: –152.3dBFS/Hz
- Single-channel mode: –155dBFS/Hz
- ENOB (dual channel, FIN = 2.4GHz): 8.8 Bits
- Noise floor (–20dBFS, VFS =
1VPP-DIFF):
- Buffered analog inputs with VCMI of 0 V:
- Analog input bandwidth (–3dB): 8GHz
- Usable input frequency range: > 10GHz
- Full-scale input voltage (VFS, default): 0.8VPP
- Noiseless aperture delay (tAD) adjustment:
- Precise sampling control: 19fs Step
- Simplifies synchronization and interleaving
- Temperature and voltage invariant delays
- Easy-to-use synchronization features:
- Automatic SYSREF timing calibration
- Timestamp for sample marking
- JESD204C serial data interface:
- Maximum lane rate: 17.16Gbps
- Support for 64b/66b and 8b/10b encoding
- 8b/10b modes are JESD204B compatible
- Optional digital down-converters (DDC):
- 4x, 8x, 16x and 32x complex decimation
- Four independent 32-Bit NCOs per DDC
- Peak RF Input Power (Diff): +26.5dBm (+ 27.5dBFS, 560x fullscale power)
- Programmable FIR filter for equalization
- Power consumption: 3.7W
- Power supplies: 1.1V, 1.9V
The ADC12DJ4000RF device is an RF-sampling, giga-sample, analog-to-digital converter (ADC) that can directly sample input frequencies from DC to above 10 GHz. ADC12DJ4000RF can be configured as a dual-channel, 4 GSPS ADC or single-channel, 8 GSPS ADC. Support of a useable input frequency range of up to 10GHz enables direct RF sampling of L-band, S-band, C-band, and X-band for frequency agile systems.
The ADC12DJ4000RF uses a high-speed JESD204C output interface with up to 16 serialized lanes supporting up to 17.16Gbps line rate. Deterministic latency and multi-device synchronization is supported through JESD204C subclass-1. The JESD204C interface can be configured to trade-off line rate and number of lanes. Both 8b/10b and 64b/66b data encoding schemes are supported. 64b/66b encoding supports forward error correction (FEC) for improved bit error rates. The interface is backwards compatible with JESD204B receivers.
Innovative synchronization features, including noiseless aperture delay adjustment and SYSREF windowing, simplify system design for multi-channel applications. Optional digital down converters (DDCs) are available to provide digital conversion to baseband and to reduce the interface rate. A programmable FIR filter allows on-chip equalization.
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技術文件
| 重要文件 | 類型 | 標題 | 格式選項 | 下載最新的英文版本 | 日期 | |
|---|---|---|---|---|---|---|
| * | 資料表 | ADC12DJ4000RF 8GSPS Single-Channel or 4GSPS Dual-Channel, 12-bit, RF-Sampling Analog-to-Digital Converter (ADC) datasheet (Rev. D) | PDF | HTML | 2025/4/8 | ||
| 應用說明 | Comparing Active vs. Passive High-Speed/RF A/D Converter Front Ends | PDF | HTML | 2025/3/28 | |||
| 應用說明 | Evaluating High-Speed, RF ADC Converter Front-end Architectures | PDF | HTML | 2025/3/26 | |||
| 技術文章 | So, what are S-parameters anyway? | PDF | HTML | 2019/5/23 |
設計與開發
如需其他條款或必要資源，請按一下下方的任何標題以檢視詳細頁面 (如有)。
ADC12DJ4000RFEVM — 適用於 4GSPS 雙通道或 8GSPS 單通道、射頻取樣、12 位元 ADC 的 ADC12DJ4000RF 評估模組
TRF1208-ADC12DJ5200RFEVM — 適用具 ADC12DJ5200RF 的高速射頻取樣全差動放大器的 TRF1208 評估模組
TI204C-IP — Request for JESD204 rapid design IP
JESD204 快速設計 IP 被設計用於幫助 FPGA 工程師快速實現可運作的 JESD204 系統，從而加速開發過程。該 IP 的架構設計使得下游數位處理和其他應用邏輯能夠隔離於 JESD204 通訊協定的大多數性能和時序關鍵約束之外。該 IP 能夠幫助設計人員減少韌體開發時間並簡化 FPGA 的整合。
JESD204 快速設計 IP 無需權利金，用於 TI 高速資料轉換器。TI 將協助使用者配置初始連結，針對特定 FPGA 平台與 TI 資料轉換器 JMODE 之間的使用進行自訂。TI 將在 IP 測試完成並準備部署後，透過安全下載連結提供 IP。
JESD204 快速設計 IP 支援下列 (...)
ADC12DJ5200RF-CALC — ADC12DJ5200RF 輸入網路全刻度計算工具。
| 封裝 | 針腳 | CAD 符號、佔位空間與 3D 模型 |
|---|---|---|
| FCCSP (ZEG) | 144 | Ultra Librarian |
| FCCSP (AAV) | 144 | Ultra Librarian |