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微控制器 (MCU) 與處理器
微處理器和 DSP
多媒體與工業網路 SoC

AM6421

現行

單核心 64 位元 Arm® Cortex®-A53、單核心 Cortex-R5F、PCIe、USB 3.0 和安全性

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產品規格表
使用指南

AM6421

現行
產品規格表 立即訂購

產品詳細資料

CPU 1 Arm Cortex-A53 Frequency (MHz) 1000 Coprocessors 2 Arm Cortex-R5F Protocols CAN FD, EtherCAT, EtherNet/IP, Ethernet, Profinet, TSN Certified protocol software stacks EtherCAT, EtherNet/IP, IO-Link, Profinet PCIe 1 PCIe Gen 2 Hardware accelerators CPU only, Industrial communications subsystem, Programable real-time unit, Security Accelerator Features Networking Operating system Linux, RTOS Security Cryptographic acceleration, Hardware-enforced isolation, Secure boot, Secure debug TI functional safety category Functional Safety-Compliant Rating Catalog Power supply solution TPS65219, TPS65220 Operating temperature range (°C) -40 to 105 Edge AI enabled Yes
CPU 1 Arm Cortex-A53 Frequency (MHz) 1000 Coprocessors 2 Arm Cortex-R5F Protocols CAN FD, EtherCAT, EtherNet/IP, Ethernet, Profinet, TSN Certified protocol software stacks EtherCAT, EtherNet/IP, IO-Link, Profinet PCIe 1 PCIe Gen 2 Hardware accelerators CPU only, Industrial communications subsystem, Programable real-time unit, Security Accelerator Features Networking Operating system Linux, RTOS Security Cryptographic acceleration, Hardware-enforced isolation, Secure boot, Secure debug TI functional safety category Functional Safety-Compliant Rating Catalog Power supply solution TPS65219, TPS65220 Operating temperature range (°C) -40 to 105 Edge AI enabled Yes
FCBGA (ALV) 441 295.84 mm² (0 mm × 0 mm)

Processor cores:

  • 1× Dual 64-bit Arm Cortex-A53 microprocessor subsystem at up to 1.0GHz
    • Dual-core Cortex-A53 cluster with 256KB L2 shared cache with SECDED ECC
    • Each A53 Core has 32KB L1 DCache with SECDED ECC and 32KB L1 ICache with Parity protection
  • Up to 2× Dual-core Arm Cortex-R5F MCU subsystems at up to 800MHz, integrated for real-time processing
    • Dual-core Arm Cortex-R5F supports dual-core and single-core modes
    • 32KB ICache, 32KB DCache and 64KB TCM per each R5F core for a total of 256KB TCM with SECDED ECC on all memories
  • 1× Single-core Arm Cortex-M4F MCU at up to 400MHz
    • 256KB SRAM with SECDED ECC

Industrial subsystem:

  • 2× gigabit Industrial Communication Subsystems (PRU_ICSSG)
    • Supports Profinet IRT, Profinet RT, EtherNet/IP, EtherCAT, Time-Sensitive Networking (TSN), and more
    • Backward compatibility with 10/100Mb PRU_ICSS
    • Each PRU_ICSSG contains:
      • 2× Ethernet ports
        • MII (10/100)
        • RGMII (10/100/1000)
      • 6 PRU RISC cores per PRU_ICSSG each core having:
        • Instruction RAM with ECC
        • Broadside RAM
        • Multiplier with optional accumulator (MAC)
        • CRC16/32 hardware accelerator
        • Byte swap for Big/Little Endian conversion
        • SUM32 hardware accelerator for UDP checksum
        • Task Manager for preemption support
      • Three Data RAMs with ECC
      • 8 banks of 30 × 32-bit register scratchpad memory
      • Interrupt controller and task manager
      • Two 64-bit Industrial Ethernet Peripherals (IEPs) for time stamping and other time synchronization functions
      • 18× Sigma-Delta filters
        • Short circuit logic
        • Over-current logic
      • 6× Multi-protocol position encoder interfaces
      • One Enhanced Capture Module (ECAP)
      • 16550-compatible UART with a dedicated 192MHz clock to support 12Mbps PROFIBUS

Memory subsystem:

  • Up to 2MB of On-chip RAM (OCSRAM) with SECDED ECC:
    • Can be divided into smaller banks in increments of 256KB for as many as 8 separate memory banks
    • Each memory bank can be allocated to a single core to facilitate software task partitioning
  • DDR Subsystem (DDRSS)
    • Supports LPDDR4, DDR4 memory types
    • 16-Bit data bus with inline ECC
    • Supports speeds up to 1600MT/s
  • 1× General-Purpose Memory Controller (GPMC)
    • 16-Bit parallel bus with 133MHz clock or
    • 32-Bit parallel bus with 100MHz clock
    • Error Location Module (ELM) support

System on Chip (SoC) Services:

  • Device Management Security Controller (DMSC-L)
    • Centralized SoC system controller
    • Manages system services including initial boot, security, and clock/reset/power management
    • Communication with various processing units over message manager
    • Simplified interface for optimizing unused peripherals

  • Data Movement Subsystem (DMSS)

    • Block Copy DMA (BCDMA)
    • Packet DMA (PKTDMA)
    • Secure Proxy (SEC_PROXY)
    • Ring Accelerator (RINGACC)

Security:

  • Secure boot supported
    • Hardware-enforced Root-of-Trust (RoT)
    • Support to switch RoT via backup key
    • Support for takeover protection, IP protection, and anti-roll back protection
  • Trusted Execution Environment (TEE) supported
    • Arm TrustZone based TEE
    • Secure watchdog/timer/IPC
    • Extensive firewall support for isolation
    • Secure storage support
    • Replay Protected Memory Block (RPMB) support
  • Security co-processor (DMSC-L) for key and security management, with dedicated device level interconnect for security
  • Cryptographic acceleration supported
    • Session-aware cryptographic engine with ability to auto-switch key-material based on incoming data stream
      • Supports cryptographic cores
    • AES – 128-/192-/256-Bit key sizes
    • SHA2 – 224-/256-/384-/512-Bit key sizes
    • DRBG with true random number generator
    • PKA (Public Key Accelerator) to Assist in RSA/ECC processing for secure boot
  • Debugging security
    • Secure software controlled debug access
    • Security aware debugging

High-speed interfaces:

  • 1× Integrated Ethernet switch (CPSW3G) supporting:
    • Up to 2 Ethernet ports
      • RMII (10/100)
      • RGMII (10/100/1000)
    • IEEE 1588 (2008 Annex D, Annex E, Annex F) with 802.1AS PTP
    • Clause 45 MDIO PHY management
    • Energy efficient Ethernet (802.3az)
  • 1× PCI-Express Gen2 controller (PCIE)
    • Supports Gen2 operation
    • Supports Single Lane operation
  • 1× USB 3.1 Dual-Role Device (DRD) Subsystem (USBSS)
    • Port configurable as USB host,USB device, orUSB Dual-Role device
    • USB device: High-speed (480Mbps), andFull-speed (12Mbps)
    • USB host: SuperSpeed Gen 1 (5Gbps),High-speed (480Mbps),Full-speed (12Mbps), andLow-speed (1.5Mbps)

General connectivity:

  • 6× Inter-Integrated Circuit (I2C) ports
  • 9× configurable Universal Asynchronous Receive/Transmit (UART) modules
  • 1× Flash Subsystem (FSS) that can be configured as Octal SPI (OSPI) flash interfaces or one Quad SPI (QSPI)
  • 1× 12-Bit Analog-to-Digital Converters (ADC)
    • Up to 4MSPS
    • 8× multiplexed analog inputs
  • 7× Multichannel Serial Peripheral Interfaces (MCSPI) controllers
  • 6× Fast Serial Interface Receiver (FSI_RX) cores
  • 2× Fast Serial Interface Transmitter (FSI_TX) cores
  • 3× General-Purpose I/O (GPIO) modules

Control interfaces:

  • 9× Enhanced Pulse-Width Modulator (EPWM) modules
  • 3× Enhanced Capture (ECAP) modules
  • 3× Enhanced Quadrature Encoder Pulse (EQEP) modules
  • 2× Modular Controller Area Network (MCAN) modules with or without full CAN-FD support

Media and data storage:

  • 2× Multi-Media Card/Secure Digital (MMC/SD/SDIO) interfaces
    • One 4-bit for SD/SDIO;
    • One 8-bit for eMMC
    • Integrated analog switch for voltage switching between 3.3V to 1.8V for high-speed cards

Power management:

  • Simplified power sequence
  • Integrated SDIO LDO for handling automatic voltage transition for SD interface
  • Integrated voltage supervisor for safety monitoring of over-under voltage conditions
  • Integrated power supply glitch detector for detecting fast supply transients

Functional Safety:

  • Functional Safety-Compliant
    • Developed for functional safety applications
    • Documentation available to aid IEC 61508 functional safety system design
    • Systematic capability up to SIL 3
    • Hardware integrity up to SIL 2
    • Safety-related certification
  • Functional Safety Features
    • ECC or parity on calculation-critical memories
    • ECC and parity on select internal bus interconnect
    • Built-In Self-Test (BIST) for CPU and on-chip RAM
    • Error Signaling Module (ESM) with error pin
    • Runtime safety diagnostics, voltage, temperature, and clock monitoring, windowed watchdog timers, CRC engine for memory integrity checks
    • Dedicated MCU domain memory, interfaces, and M4F core capable of being isolated from the larger SoC with Freedom From Interference (FFI) features
      • Separate interconnect
      • Firewalls and timeout gaskets
      • Dedicated PLL
      • Dedicated I/O supply
      • Separate reset

SoC architecture:

  • Supports primary boot from UART, I2C, OSPI/QSPI Flash, SPI Flash, parallel NOR Flash, parallel NAND Flash, SD, eMMC, USB, PCIe, and Ethernet interfaces
  • 16nm FinFET technology

Package options:

  • ALV: 17.2mm × 17.2mm, 0.8mm pitch, 441-pin BGA package
  • ANI: 17.2mm × 17.2mm, 0.8mm pitch, 441-pin BGA package

Processor cores:

  • 1× Dual 64-bit Arm Cortex-A53 microprocessor subsystem at up to 1.0GHz
    • Dual-core Cortex-A53 cluster with 256KB L2 shared cache with SECDED ECC
    • Each A53 Core has 32KB L1 DCache with SECDED ECC and 32KB L1 ICache with Parity protection
  • Up to 2× Dual-core Arm Cortex-R5F MCU subsystems at up to 800MHz, integrated for real-time processing
    • Dual-core Arm Cortex-R5F supports dual-core and single-core modes
    • 32KB ICache, 32KB DCache and 64KB TCM per each R5F core for a total of 256KB TCM with SECDED ECC on all memories
  • 1× Single-core Arm Cortex-M4F MCU at up to 400MHz
    • 256KB SRAM with SECDED ECC

Industrial subsystem:

  • 2× gigabit Industrial Communication Subsystems (PRU_ICSSG)
    • Supports Profinet IRT, Profinet RT, EtherNet/IP, EtherCAT, Time-Sensitive Networking (TSN), and more
    • Backward compatibility with 10/100Mb PRU_ICSS
    • Each PRU_ICSSG contains:
      • 2× Ethernet ports
        • MII (10/100)
        • RGMII (10/100/1000)
      • 6 PRU RISC cores per PRU_ICSSG each core having:
        • Instruction RAM with ECC
        • Broadside RAM
        • Multiplier with optional accumulator (MAC)
        • CRC16/32 hardware accelerator
        • Byte swap for Big/Little Endian conversion
        • SUM32 hardware accelerator for UDP checksum
        • Task Manager for preemption support
      • Three Data RAMs with ECC
      • 8 banks of 30 × 32-bit register scratchpad memory
      • Interrupt controller and task manager
      • Two 64-bit Industrial Ethernet Peripherals (IEPs) for time stamping and other time synchronization functions
      • 18× Sigma-Delta filters
        • Short circuit logic
        • Over-current logic
      • 6× Multi-protocol position encoder interfaces
      • One Enhanced Capture Module (ECAP)
      • 16550-compatible UART with a dedicated 192MHz clock to support 12Mbps PROFIBUS

Memory subsystem:

  • Up to 2MB of On-chip RAM (OCSRAM) with SECDED ECC:
    • Can be divided into smaller banks in increments of 256KB for as many as 8 separate memory banks
    • Each memory bank can be allocated to a single core to facilitate software task partitioning
  • DDR Subsystem (DDRSS)
    • Supports LPDDR4, DDR4 memory types
    • 16-Bit data bus with inline ECC
    • Supports speeds up to 1600MT/s
  • 1× General-Purpose Memory Controller (GPMC)
    • 16-Bit parallel bus with 133MHz clock or
    • 32-Bit parallel bus with 100MHz clock
    • Error Location Module (ELM) support

System on Chip (SoC) Services:

  • Device Management Security Controller (DMSC-L)
    • Centralized SoC system controller
    • Manages system services including initial boot, security, and clock/reset/power management
    • Communication with various processing units over message manager
    • Simplified interface for optimizing unused peripherals

  • Data Movement Subsystem (DMSS)

    • Block Copy DMA (BCDMA)
    • Packet DMA (PKTDMA)
    • Secure Proxy (SEC_PROXY)
    • Ring Accelerator (RINGACC)

Security:

  • Secure boot supported
    • Hardware-enforced Root-of-Trust (RoT)
    • Support to switch RoT via backup key
    • Support for takeover protection, IP protection, and anti-roll back protection
  • Trusted Execution Environment (TEE) supported
    • Arm TrustZone based TEE
    • Secure watchdog/timer/IPC
    • Extensive firewall support for isolation
    • Secure storage support
    • Replay Protected Memory Block (RPMB) support
  • Security co-processor (DMSC-L) for key and security management, with dedicated device level interconnect for security
  • Cryptographic acceleration supported
    • Session-aware cryptographic engine with ability to auto-switch key-material based on incoming data stream
      • Supports cryptographic cores
    • AES – 128-/192-/256-Bit key sizes
    • SHA2 – 224-/256-/384-/512-Bit key sizes
    • DRBG with true random number generator
    • PKA (Public Key Accelerator) to Assist in RSA/ECC processing for secure boot
  • Debugging security
    • Secure software controlled debug access
    • Security aware debugging

High-speed interfaces:

  • 1× Integrated Ethernet switch (CPSW3G) supporting:
    • Up to 2 Ethernet ports
      • RMII (10/100)
      • RGMII (10/100/1000)
    • IEEE 1588 (2008 Annex D, Annex E, Annex F) with 802.1AS PTP
    • Clause 45 MDIO PHY management
    • Energy efficient Ethernet (802.3az)
  • 1× PCI-Express Gen2 controller (PCIE)
    • Supports Gen2 operation
    • Supports Single Lane operation
  • 1× USB 3.1 Dual-Role Device (DRD) Subsystem (USBSS)
    • Port configurable as USB host,USB device, orUSB Dual-Role device
    • USB device: High-speed (480Mbps), andFull-speed (12Mbps)
    • USB host: SuperSpeed Gen 1 (5Gbps),High-speed (480Mbps),Full-speed (12Mbps), andLow-speed (1.5Mbps)

General connectivity:

  • 6× Inter-Integrated Circuit (I2C) ports
  • 9× configurable Universal Asynchronous Receive/Transmit (UART) modules
  • 1× Flash Subsystem (FSS) that can be configured as Octal SPI (OSPI) flash interfaces or one Quad SPI (QSPI)
  • 1× 12-Bit Analog-to-Digital Converters (ADC)
    • Up to 4MSPS
    • 8× multiplexed analog inputs
  • 7× Multichannel Serial Peripheral Interfaces (MCSPI) controllers
  • 6× Fast Serial Interface Receiver (FSI_RX) cores
  • 2× Fast Serial Interface Transmitter (FSI_TX) cores
  • 3× General-Purpose I/O (GPIO) modules

Control interfaces:

  • 9× Enhanced Pulse-Width Modulator (EPWM) modules
  • 3× Enhanced Capture (ECAP) modules
  • 3× Enhanced Quadrature Encoder Pulse (EQEP) modules
  • 2× Modular Controller Area Network (MCAN) modules with or without full CAN-FD support

Media and data storage:

  • 2× Multi-Media Card/Secure Digital (MMC/SD/SDIO) interfaces
    • One 4-bit for SD/SDIO;
    • One 8-bit for eMMC
    • Integrated analog switch for voltage switching between 3.3V to 1.8V for high-speed cards

Power management:

  • Simplified power sequence
  • Integrated SDIO LDO for handling automatic voltage transition for SD interface
  • Integrated voltage supervisor for safety monitoring of over-under voltage conditions
  • Integrated power supply glitch detector for detecting fast supply transients

Functional Safety:

  • Functional Safety-Compliant
    • Developed for functional safety applications
    • Documentation available to aid IEC 61508 functional safety system design
    • Systematic capability up to SIL 3
    • Hardware integrity up to SIL 2
    • Safety-related certification
  • Functional Safety Features
    • ECC or parity on calculation-critical memories
    • ECC and parity on select internal bus interconnect
    • Built-In Self-Test (BIST) for CPU and on-chip RAM
    • Error Signaling Module (ESM) with error pin
    • Runtime safety diagnostics, voltage, temperature, and clock monitoring, windowed watchdog timers, CRC engine for memory integrity checks
    • Dedicated MCU domain memory, interfaces, and M4F core capable of being isolated from the larger SoC with Freedom From Interference (FFI) features
      • Separate interconnect
      • Firewalls and timeout gaskets
      • Dedicated PLL
      • Dedicated I/O supply
      • Separate reset

SoC architecture:

  • Supports primary boot from UART, I2C, OSPI/QSPI Flash, SPI Flash, parallel NOR Flash, parallel NAND Flash, SD, eMMC, USB, PCIe, and Ethernet interfaces
  • 16nm FinFET technology

Package options:

  • ALV: 17.2mm × 17.2mm, 0.8mm pitch, 441-pin BGA package
  • ANI: 17.2mm × 17.2mm, 0.8mm pitch, 441-pin BGA package

AM64x is an extension of the Sitara™ Industrial-grade family of heterogeneous Arm® processors. AM64x is built for industrial applications, such as motor drives and Programmable Logic Controllers (PLCs), which require a unique combination of real-time processing and communications with applications processing. AM64x combines two instances of the Sitara device’s gigabit TSN-enabled PRU-ICSSG with up to two Arm® Cortex®-A53 cores, up to four Cortex-R5F MCUs, and a Cortex-M4F MCU.

AM64x is architected to provide real-time performance through the high-performance R5Fs, Tightly-Coupled Memory banks, configurable SRAM partitioning, and dedicated low-latency paths to and from peripherals for rapid data movement in and out of the SoC. This deterministic architecture allows for AM64x to handle the tight control loops found in servo drives while the peripherals like FSI, GPMC, PWMs, sigma delta decimation filters, and absolute encoder interfaces help enable a number of different architectures found in these systems.

The Cortex-A53s provide the powerful computing elements necessary for Linux applications. Linux, and Real-time (RT) Linux, is provided through TI’s Processor SDK Linux which stays updated to the latest Long Term Support (LTS) Linux kernel, bootloader and Yocto file system on an annual basis. AM64x helps bridge the Linux world with the real-time world by enabling isolation between Linux applications and real-time streams through configurable memory partitioning. The Cortex-A53s can be assigned to work strictly out of DDR for Linux, and the internal SRAM can be broken up into various sizes for the Cortex-R5Fs to use together or independently.

The AM64x provides flexible industrial communications capability including full protocol stacks for EtherCAT SubDevice, PROFINET device, EtherNet/IP adapter, and IO-Link Master. The PRU-ICSSG further provides capability for gigabit and TSN based protocols. In addition, the PRU-ICSSG also enables additional interfaces in the SoC including sigma delta decimation filters and absolute encoder interfaces.

Functional safety features can be enabled through the integrated Cortex-M4F along with dedicated peripherals which can all be isolated from the rest of the SoC. AM64x also supports secure boot.

AM64x is an extension of the Sitara™ Industrial-grade family of heterogeneous Arm® processors. AM64x is built for industrial applications, such as motor drives and Programmable Logic Controllers (PLCs), which require a unique combination of real-time processing and communications with applications processing. AM64x combines two instances of the Sitara device’s gigabit TSN-enabled PRU-ICSSG with up to two Arm® Cortex®-A53 cores, up to four Cortex-R5F MCUs, and a Cortex-M4F MCU.

AM64x is architected to provide real-time performance through the high-performance R5Fs, Tightly-Coupled Memory banks, configurable SRAM partitioning, and dedicated low-latency paths to and from peripherals for rapid data movement in and out of the SoC. This deterministic architecture allows for AM64x to handle the tight control loops found in servo drives while the peripherals like FSI, GPMC, PWMs, sigma delta decimation filters, and absolute encoder interfaces help enable a number of different architectures found in these systems.

The Cortex-A53s provide the powerful computing elements necessary for Linux applications. Linux, and Real-time (RT) Linux, is provided through TI’s Processor SDK Linux which stays updated to the latest Long Term Support (LTS) Linux kernel, bootloader and Yocto file system on an annual basis. AM64x helps bridge the Linux world with the real-time world by enabling isolation between Linux applications and real-time streams through configurable memory partitioning. The Cortex-A53s can be assigned to work strictly out of DDR for Linux, and the internal SRAM can be broken up into various sizes for the Cortex-R5Fs to use together or independently.

The AM64x provides flexible industrial communications capability including full protocol stacks for EtherCAT SubDevice, PROFINET device, EtherNet/IP adapter, and IO-Link Master. The PRU-ICSSG further provides capability for gigabit and TSN based protocols. In addition, the PRU-ICSSG also enables additional interfaces in the SoC including sigma delta decimation filters and absolute encoder interfaces.

Functional safety features can be enabled through the integrated Cortex-M4F along with dedicated peripherals which can all be isolated from the rest of the SoC. AM64x also supports secure boot.
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技術文件

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重要文件 類型 標題 格式選項 下載最新的英文版本 日期
* 資料表 AM64x Sitara™ Processors datasheet (Rev. J) PDF | HTML 2026/6/11
* 使用指南 AM64x/AM243x Technical Reference Manual (Rev. J) PDF | HTML 2026/5/8
* 勘誤表 AM64x/AM243x Processor Silicon Revision 1.0, 2.0 (Rev. J) PDF | HTML 2025/11/13
白皮書 Securing the Future: Cyber Resilience Act (EU-CRA) Compliance with TI’s Jacinto and Sitara Processors PDF | HTML 2026/4/24
應用說明 Custom Board Design and Simulation Guidelines for Processor High Speed Parallel Interfaces (Rev. A) PDF | HTML 2026/2/12
應用說明 Enabling Matter on Sitara MPU (Rev. A) PDF | HTML 2025/11/24
應用說明 Getting Started with Sysconfig Tool PDF | HTML 2025/11/21
使用指南 Hardware Design Considerations for Custom Board Using AM6442, AM6422, AM6412 and AM2434 (ALV, ALX) Processor (Rev. D) PDF | HTML 2025/10/24
應用說明 Sitara Processor Power Distribution Networks: Implementation and Analysis (Rev. H) PDF | HTML 2025/10/17
使用指南 AM6442 , AM6422 , AM6412 and AM2434 Processor Schematic Design Guidelines and Schematic Review Checklist (Rev. E) PDF | HTML 2025/10/10
應用說明 Industrial Communication Protocols Supported on TI Processors and MCUs (Rev. F) PDF | HTML 2025/9/3
功能安全資訊 AM6x, AM24x Software Diagnostics Library TÜV SÜD Functional Safety Certificate for 9.2.0 SDK (Rev. A) 2025/7/17
應用說明 Processors Tools Overview PDF | HTML 2025/6/16
白皮書 Securing Arm-Based Application Processors (Rev. F) PDF | HTML 2025/2/26
應用說明 Basic Ethernet Interface Debug With Linux PDF | HTML 2024/10/11
白皮書 Functional Safety Support for Arm®-based Microcontrollers and Processors (Rev. A) PDF | HTML 2024/5/10
功能安全資訊 AM64x, AM243x IEC61508 TUV SUD Functional Safety Certificate 2024/3/25
應用說明 Sitara™AM64x /AM243x BenchmarksCortex-R5 Memory Access Latency (Rev. B) PDF | HTML 2024/1/24
Product overview Industrial Communication Protocol Support for Arm®-based Microcontrollers and Processors PDF | HTML 2023/12/22
應用說明 Using TSN Ethernet Features to Improve Timing in Industrial Ethernet Controllers PDF | HTML 2023/11/15
應用說明 Integration of MbedTLS on SITARA MCU Devices PDF | HTML 2023/8/3
應用說明 Intra Drive Communication Using 8b-10b Line Code With Programmable Real Time Uni PDF | HTML 2023/5/24
應用說明 High-Speed Interface Layout Guidelines (Rev. J) PDF | HTML 2023/2/24
應用說明 PRU-ICSS Feature Comparison (Rev. G) PDF | HTML 2022/10/11
應用說明 Powering the AM64x with the TPS65220 or TPS65219 PMIC PDF | HTML 2022/9/22
應用說明 Optimized Trigonometric Functions on TI Arm Cores (Rev. A) PDF | HTML 2022/8/8
應用說明 AM64x/AM243x Extended Power-On Hours PDF | HTML 2022/8/5
Product overview Voltage Translation Application Quick Reference PDF | HTML 2022/6/28
應用說明 AM243x/AM64x Single Chip Motor Control Benchmark PDF | HTML 2022/3/30
應用說明 Using LP8733xx and TPS65218xx PMICs to Power AM64x and AM243x Sitara Processors PDF | HTML 2022/2/16
更多文件說明 Quick Start Guide for Wi-SUN® Wireless MCUs and Transceivers PDF | HTML 2022/1/14
Application brief Powering the AM64xx With the LP8733xx PMIC PDF | HTML 2021/7/15
應用說明 AM64x/AM243x DDR Board Design and Layout Guidelines (Rev. A) PDF | HTML 2021/7/1
應用說明 AM64x/AM243x Power Estimation Tool (Rev. A) PDF | HTML 2021/7/1
使用指南 AM64x/AM243x BGA Escape Routing (Rev. A) PDF | HTML 2021/4/6
更多文件說明 Decentralized servo architecture webinar 2021/3/1
技術文章 Compact. Precise. Connected. Increase productivity with intelligent edge computing PDF | HTML 2021/2/1
更多文件說明 From Start to Finish: A Product Development Roadmap for Sitara™ Processors 2020/12/16

設計與開發

電源供應解決方案

為 AM6421 尋找可用的電源供應解決方案。TI 提供適用於 TI 與非 TI 之系統單晶片 (SoC)、處理器、微控制器、感測器或現場可編程邏輯閘陣列 (FPGA) 的電源供應解決方案。

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開發板

SK-AM64B — 適用於 AM64x Sitara™ 處理器的 AM64B 入門套件

AM64B 入門套件 (SK) 為低成本的獨立式測試與開發平台，其以 Sitara™ AM6442 處理器為基礎，是加快未來設計原型階段的理想選擇。此套件包含有線 (乙太網路) 和無線 (2.4GHz 和 5GHz) 連線、三個擴充接頭、多個開機選項及彈性偵錯功能。

在自訂電路板設計時，客戶傾向於重複使用 SK 設計檔案並對該設計檔案進行編輯。或者，客戶會重複使用部分常見的實作，包括 SOC、記憶體和通訊介面。由於 SK 應具備額外功能，所以客戶會針對其主機板設計需求將 SK 實作最佳化。將 SK (...)

使用指南: PDF | HTML
支援產品和硬體
開發板

TMDS64DC01EVM — AM64x IO-Link 和高速分接板

The AM64x IO-Link and high speed expansion board is an add-on module for the AM64x GP EVM.  This board includes eight (8) IO-Link ports and general purpose signal breakout.  The Breakout board section provides the test access to all the IO signals included on the High Speed Expansion (...)

使用指南: PDF | HTML
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開發板

TMDS64EVM — 適用 Sitara™ 處理器的 AM64x 評估模組

TMDS64 評估模組 (EVM) 為獨立的測試與開發平台，是加快未來設計原型階段的理想選擇。  TMDS64EVM 配備了 Sitara™ AM6442 處理器及其他零組件，可讓使用者使用各種裝置介面，其中包括工業乙太網路、標準乙太網路、快捷週邊設備元件互連 (PCIe)、快速序列介面 (FSI) 及其他功能，可輕鬆建立原型。
車載顯示器使用 AM64x 序列周邊介面 (SPI) 連接埠，除了 LED 外也提供本機視覺輸出的能力。板載電流測量功能可用於監控節能應用的功耗。

在自訂電路板設計時，客戶傾向於重複使用 SK 設計檔案並對該設計檔案進行編輯。或者，客戶會重複使用部分常見的實作，包括 (...)

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開發板

PHYTC-3P-KIT-AM64 — phyBOARD®-AM64x 開發套件

phyBOARD®-AM64x 開發套件是一款系統模組 (SOM) 和載板，採用 phyCORE®-AM64x，這是一款強大且可靠的嵌入式處理器板，適用於無顯示工業通訊系統。50 mm x 37 mm SOM 具有廣泛的 280 接腳互連，可支援常見工廠通訊協定 (如 CAN、EtherCAT、UART、I2C)，也支援自動化特定介面 (如 EPWM、ECAP 及 EQEP)。由於 TI AM64x 處理器的異質架構，您可使用 Linux 執行大部分應用程式，並將關鍵元件卸載至專業低延遲同級最佳即時核心。

從：PHYTEC
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開發板

TQ-3P-SITARASOMS — 適用於 TI Arm 架構處理器和微控制器的 TQ Group 系統模組

TQ offers the complete range of services from development, through production and service right up to product life cycle management. The services cover assemblies, equipment and systems including hardware, software and mechanics. Customers can obtain all services from TQ on a modular basis as (...)
從：TQ-Group
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開發板

TQ-3P-SOM-TQMA64XXL — TQ-Group TQMa64xxL system on module for AM6442 processor

The embedded module TQMa64xxL is based on the AM64x processor family. This land grid array (LGA) module is designed to use the pin compatible processors on one module design. This module is ideally suited for headless applications with extended real-time requirements. The CPU offers integrated (...)

從：TQ-Group
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開發板

TRONL-3P-SOM-TL64 — 適用於 TI AM64x 64 位元 Arm 架構處理器的 Tronlong 系統模組

廣州創龍電子科技有限公司成立於 2013 年，是一家嵌入式產品平台供應商，致力於建立高品質的工業核心電路板，以及評估套件與專案服務。Tronlong 總部設在廣州科學城，擁有獨立營運的教育儀器設備業務部門，並在北京、上海、深圳和西安等地設立辦事處。

Tronlong 著重於 DSP 與 Arm® 架構處理器開發，擁有以 TI 裝置為基礎的廣泛產品組合。產品廣泛用於工業自動化、儀器、能源與電力、通訊及醫療產業。憑藉「提供高可靠性產品並快速回應客戶需求和有效解決問題」的使命宣言，Tronlong 已成功幫助 10,000 多家企業、研究機構和大學完成產品的開發和上市。

從：Guangzhou Tronlong Electronic Technology Co., Ltd.
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偵錯探測器

TMDSEMU110-U — XDS110 JTAG 偵錯探測器

德州儀器 XDS110 是一種全新的偵錯探測器 (模擬器) 類別，適用於 TI 嵌入式處理器。XDS110 取代 XDS100 系列，可在單一 Pod 中支援更廣泛的標準 (IEEE1149.1、IEEE1149.7、SWD)。同時，所有 XDS 偵錯探針在所有配備嵌入式追蹤緩衝器 (ETB) 的 Arm® 與 DSP 處理器中均支援核心與系統追蹤。  對於針腳上的核心追蹤，則需要 XDS560v2 PRO TRACE。

德州儀器 XDS110 透過 TI 20 針腳連接器（具有用於 TI 14 針腳和 Arm 10 針腳和 Arm 20 針腳的多轉接器）連接到目標電路板，並透過 USB2.0 (...)

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偵錯探測器

TMDSEMU200-U — XDS200 USB 偵錯探測器

XDS200 是為 TI 嵌入式裝置偵錯的偵錯探測器（模擬器）。對於大多數裝置，建議使用較新、成本較低的 XDS110 (www.ti.com/tool/TMDSEMU110-U)。XDS200 支援單一 Pod 中廣泛的標準（IEEE1149.1、IEEE1149.7、SWD）。所有 XDS 偵錯探針在所有配備嵌入式追蹤緩衝器 (ETB) 的 Arm® 與 DSP 處理器中均支援核心與系統追蹤。

XDS200 透過 TI 20 接腳連接器（配備適用 TI 14 接腳、Arm Cortex® 10 接腳和 Arm 20 接腳的多重轉接器）連接到目標電路板，並透過 USB2.0 高速 (...)

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偵錯探測器

TMDSEMU560V2STM-U — XDS560™ 軟體 v2 系統追蹤 USB 偵錯探測器

XDS560v2 是 XDS560™ 系列偵錯探測器中性能最高的，且同時支援傳統 JTAG 標準 (IEEE1149.1) 與 cJTAG (IEEE1149.7)。  請注意，其不支援序列線偵錯 (SWD)。

所有 XDS 偵錯探測器均在所有配備嵌入式追蹤緩衝器 (ETB) 的 ARM 與 DSP 處理器中支援核心與系統追蹤。  對於針腳上的追蹤，則需要 XDS560v2 PRO TRACE。

XDS560v2 透過 MIPI HSPT 60 針腳接頭 (具有用於 TI 14 針腳、TI 20 針腳和 ARM 20 針腳的多轉接器) 連接到目標電路板，並透過 USB2.0 高速 (...)

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偵錯探測器

TMDSEMU560V2STM-UE — XDS560v2 System Trace USB 與乙太網路偵錯探測器

The XDS560v2 is the highest performance of the XDS560™ family of debug probes and supports both the traditional JTAG standard (IEEE1149.1) and cJTAG (IEEE1149.7). Note that it does not support serial wire debug (SWD).

All XDS debug probes support Core and System Trace in all ARM and DSP processors (...)

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偵錯探測器

LB-3P-TRACE32-ARM — 適用於 Arm® 架構微控制器和處理器的 Lauterbach TRACE32® 偵錯和追蹤系統

Lauterbach 的 TRACE32® 工具是一套先進的軟硬體元件，可讓開發人員分析、最佳化及認證各種 Arm® 架構微控制器和處理器。全球知名的嵌入式系統和 SoC 偵錯和追蹤解決方案是完美的解決方案，適用於從早期的矽前 (pre-silicon) 開發，到產品認證和現場故障排除等所有開發階段。Lauterbach 工具的直覺模組化設計為工程師提供現今最高的可用性能，以及可隨需求變化而調整和成長的系統。藉由 TRACE32® 偵錯器，開發人員也可透過單一偵錯介面，同時偵錯和控制 SoC 中的任何 C28x/C29x/C6x/C7x DSP 核心及所有其他 Arm (...)

從：Lauterbach GmbH
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偵錯探測器

TSK-3P-BLUEBOX — TASKING BlueBox hardware debugger

TASKING’s Debug, Trace, and Test tools offer comprehensive solutions for efficient debugging, tracing, and testing of TI's embedded systems. The scalable TASKING BlueBox debuggers allow users to easily flash, debug, and test across TI's portfolio. Development on TI hardware is made even easier with (...)

從：TASKING Germany GmbH
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軟體開發套件 (SDK)

INDUSTRIAL-COMMUNICATIONS-SDK-AM64X — Industrial Communications SDK for AM64x

這款軟體開發套件 (SDK) 包含 TI 處理器上的即時工業通訊協定 (EtherCAT、EtherNet/IP、PROFINET、IO-Link 等)。此外也具備 PRU-ICSS 韌體、驅動程式、通訊堆疊函式庫和應用範例，以及相關文件。

新功能：

  • 透過 EtherCAT EoE 的乙太網路
  • 透過 EtherCAT FoE 存取檔案
  • 整合 NVM 資料庫以持續儲存資料 — EtherCAT 範例現在使用 EEPROM 來儲存 EtherCAT EEPROM 資料，而非使用快閃記憶體
  • Ethernet/IP — 物件字典大小應可在無需重新建立堆疊的情況下進行變更
  • IOLINK 控制器 — (...)
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軟體開發套件 (SDK)

MCU-PLUS-SDK-AM64X — MCU+ SDK for AM64x – RTOS, No-RTOS

處理器和 MCU+ SDK (軟體開發套件) 是用於 TI 嵌入式處理器的統合軟體平台，可提供簡易設定及迅速且立即執行基準測試與示範。這些 SDK 的所有版本在 TI 為其提供的廣泛產品組合中都是一致的，開發人員能順暢地在其他裝置上重複使用軟體，並開發軟體。提供軟體組建表以幫助將硬體功能對應到目前和未來 SDK 中的軟體可用性，以進行專案規劃。

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軟體開發套件 (SDK)

PROCESSOR-SDK-LINUX-AM64X — Processor SDK Linux for AM64x

處理器和 MCU+ SDK (軟體開發套件) 是用於 TI 嵌入式處理器的統合軟體平台，可提供簡易設定及迅速且立即執行基準測試與示範。這些 SDK 的所有版本在 TI 為其提供的廣泛產品組合中都是一致的，開發人員能順暢地在其他裝置上重複使用軟體，並開發軟體。提供軟體組建表以幫助將硬體功能對應到目前和未來 SDK 中的軟體可用性，以進行專案規劃。

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軟體開發套件 (SDK)

PROCESSOR-SDK-LINUX-RT-AM64X — Processor SDK RT-Linux for AM64x

處理器和 MCU+ SDK (軟體開發套件) 是用於 TI 嵌入式處理器的統合軟體平台，可提供簡易設定及迅速且立即執行基準測試與示範。這些 SDK 的所有版本在 TI 為其提供的廣泛產品組合中都是一致的，開發人員能順暢地在其他裝置上重複使用軟體，並開發軟體。提供軟體組建表以幫助將硬體功能對應到目前和未來 SDK 中的軟體可用性，以進行專案規劃。

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軟體開發套件 (SDK)

IBV-3P-ICECAT — 適用於嵌入式系統的 IBV EtherCAT MainDevice SDK

The icECAT EtherCAT Master Stack library by IBV is a Software Development Kit (SDK) for creating an EtherCAT MainDevice (master) system achieving best performance with lowest resource usage. It is especially designed for use on embedded systems with optimized Link Layer drivers with DMA support (...)

從：IBV - Echtzeit- und Embedded GmbH & Co. KG
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IDE、配置、編譯器或偵錯程式

CCSTUDIO — Code Composer Studio™ integrated development environment (IDE)

CCStudio™ IDE is part of TI's extensive CCStudio™ development ecosystem and is an integrated development environment for TI's microcontrollers, processors, wireless connectivity devices, and radar sensors. CCStudio IDE is available as desktop or cloud-based applications. The cloud version (...)

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IDE、配置、編譯器或偵錯程式

CLOCKTREE-AM64X — Clock tree configuration for AM64x

The Clock Tree Tool (CTT) for Sitara™ ARM®, Automotive, and Digital Signal Processors is an interactive clock tree configuration software that provides information about the clocks and modules in these TI devices. It allows the user to:

  • Visualize the device clock tree
  • Interact with clock tree (...)
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IDE、配置、編譯器或偵錯程式

DDR-CONFIG-AM64 — DDR Configuration Tool

This SysConfig based tool simplifies the process of configuring the DDR Subsystem Controller and PHY to interface to SDRAM devices. Based on the memory device, board design, and topology the tool outputs files to initialize and train the selected memory.
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IDE、配置、編譯器或偵錯程式

K3-RESOURCE-CONFIGURATION — Resource partitioning tool for multi core SOCs

Also known as the k3-respart-tool, the Resource Configuration tool allows for configuration of various system level parameters and generate the necessary data to be fed into software components
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IDE、配置、編譯器或偵錯程式

SYSCONFIG — Standalone desktop version of SysConfig

CCStudio™ SysConfig is part of TI's extensive CCStudio™ development ecosystem and is a configuration tool that simplifies hardware and software configuration challenges to accelerate software development.

SysConfig provides an intuitive graphical user interface for configuring pins, peripherals, (...)

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線上培訓

AM64-ACADEMY — AM64x Academy

Designed to simplify and accelerate custom AM64x development.
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快速入門

TI-DEVELOPER-ZONE — Start embedded development on your desktop or in the cloud

From evaluation to deployment the TI Developer Zone provides a comprehensive range of software, tools and training to ensure that you have everything you need for each stage of the development process.
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作業系統 (OS)

GHS-INTEGRITY-RTOS — Green Hills INTEGRITY RTOS

The flagship of Green Hills Software operating systems—the INTEGRITY RTOS—is built around a partitioning architecture to provide embedded systems with total reliability, absolute security, and maximum real-time performance. With its leadership pedigree underscored by certifications in a (...)
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作業系統 (OS)

GHS-3P-UVELOSITY — Green Hills Software u-velOSity Safety RTOS

The µ-velOSity™ Safety RTOS is the smallest of Green Hills Software's real-time operating systems and was designed especially for microcontrollers. It supports a wide range of TI processor families using the Arm® Cortex-M or Cortex-R cores as a main CPU or as a co-processors (...)

從：Green Hills Software
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作業系統 (OS)

TRZN-3P-TORIZON-OS — Torizon OS 開箱即用的工業級嵌入式 Linux 發行版

Torizon OS 是一個免費的開放原始碼工業級嵌入式 Linux 作業系統，致力於簡化需要高可靠性和安全性的產品的開發和維護。除其他重要服務外，它還具備優化的容器執行時和可實現安全的離綫與遠程無線 (OTA) 更新，裝置監控和遠程存取的元件。Torizon OS 能透過簡單的客製化在您的硬體上直接使用，並預設為安全狀態，提供頻繁的更新和易於操作的簡易安全功能。Torizon OS 基於開放式軟體，沒有鎖定，完全免費，包括 Toradex 系統模組 (SoM) 的頻繁更新。利用 Torizon OS 簡化開發和網路安全合規性。

從：Torizon
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作業系統 (OS)

WHIS-3P-SAFERTOS — WITTENSTEIN SAFERTOS 預先認證的安全 RTOS

SAFERTOS® 是專為嵌入式處理器設計的獨特即時作業系統。經 TÜV SÜD 預先認證，符合 IEC 61508 SIL3 與 ISO 26262 ASILD 標準。SAFERTOS® 是由 WHIS 專家團隊專為安全而打造，適用於全球重要安全應用。WHIS 與德州儀器的合作已經超過十年。在此期間，WHIS 已將 SAFERTOS® 移植至各種 TI 處理器，支援所有熱門核心，並可依要求提供其他架構。SAFERTOS® 專為您的特定處理器/編譯器組合量身打造，隨附完整的原始程式碼與設計保證包，可完全一目了然整個設計生命週期。許多 WHIS 客戶開始使用 FreeRTOS (...)

從：WITTENSTEIN High Integrity Systems
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韌體

DDR-MARGIN-FW — Firmware and scripts to measure system DDR margin

The DDR margin firmware and supporting scripts allow visualization and measurement of system margin in the DDR interface on board. These tools enable probe-less measurement of critical data signals to understand the integrity and robustness of the interface.
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韌體

USIT-3P-SECIC-HSM — Uni-Sentry SecIC-HSM 韌體

SecIC-HSM 旨在滿足 MCU/SoC 晶片所需的網路安全要求。HSM 韌體可應用於汽車、新能源、光伏、機器人、醫療保健與航空等領域。提供的網路安全功能包括安全開機、安全通訊 (SecOC)、安全診斷、安全儲存、安全更新、安全偵錯和金鑰管理。SecIC-HSM 的優點：一站式網路安全解決方案，具備跨晶片系列的全方位軟體相容性，擁有業界領先的性能，已在近 30 家 OEM 的量產車型中成功部署，累計出貨超過 300 萬套。

從：Shanghai Uni-Sentry Intelligent Technology Co., LTD
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韌體

USIT-3P-SECIC-PQC — Uni-Sentry SecIC-PQC 演算法韌體

Uni-Sentry 的安全解決方案採用 PQC 演算法，能夠抵抗量子電腦對傳統加密演算法所造成的解密威脅。PQC 韌體與硬體安全模組 (HSM) 進行協同優化，利用硬體加速與安全性強化，以提升加密演算法的執行效率與安全性。 


Uni-Sentry 持續監控全球量子運算的發展，並更新其演算法組合。當前的 PQC 產品功能包括：

  • SP 800-208：LMS 和 XMSS
  • FIPS 203 (ML-KEM)：CRYSTALS-KYBER
  • FIPS 204 (ML-DSA)：CRYSTALS-Dilithium
  • FIPS 205 (SLH-DSA)： SPHINCS+ 

技術亮點 

  • 量子抗性認證：與 (...)
從：Shanghai Uni-Sentry Intelligent Technology Co., LTD
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支援軟體

VLAB-3P-V-EVM — ASTC VLAB 虛擬開發平台和工具

VLAB Works 是嵌入式電子系統建模、模擬和虛擬原型設計軟體技術的業界領導者。VLAB 技術和解決方案有助於在開發嵌入式系統時，應用自動化和敏捷流程。VLAB Works 協助客戶設計更佳的產品、更有效率地進行開發、減少對製造和硬體的需求，且可協助對地球更環保。VLAB 模擬為現成可用，適用於各種 TI SoC，並且可根據客戶需求提供其他模型。適用於 TI SoC 的模擬平台已經過驗證，且在 TI.com 上提供相關的處理器 SDK。

從：VLAB Works
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模擬型號

AM243x and AM64x ALV SR 2.0 BSDL Model

SPRM811.ZIP (21 KB) - BSDL 模型
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模擬型號

AM243x and AM64x ALV SR 2.0 IBIS Model

SPRM810.ZIP (1889 KB) - IBIS 模型
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模擬型號

AM243x and AM64x ALV SR 2.0 IBIS-AMI Model

SPRM731.ZIP (44474 KB) - IBIS-AMI 模型
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模擬型號

AM243x and AM64x ALV SR 2.0 Thermal Model (Rev. A)

SPRM773A.ZIP (1 KB) - 熱模型
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計算工具

AM64-PET-CALC — AM64 功率估計工具

AM64 PET provides power consumption estimates based on measured and simulated data; they are provided “as is” and are not guaranteed within a specified precision.
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計算工具

SPRM779 — AM64x Power Estimation Tool

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計算工具

SPRR451 — AM64x Maximum Current Ratings

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封裝 針腳 CAD 符號、佔位空間與 3D 模型
FCBGA (ALV) 441 Ultra Librarian
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