CDCE6214
- Configurable high performance, low-power, frac-N PLL with RMS jitter with spurs (12 kHz – 20 MHz, Fout > 100 MHz) as:
- Integer mode:
- Differential output: 350 fs typical, 600 fs maximum
- LVCMOS output: 1.05 ps typical, 1.5 ps maximum
- Fractional mode:
- Differential output: 1.7 ps typical, 2.1 ps maximum
- LVCMOS output: 2.0 ps typical, 4.0 ps maximum
- Integer mode:
- Supports PCIe Gen1/2/3/4 with SSC and Gen 1/2/3/4/5 without SSC
- 2.335-GHz to 2.625-GHz internal VCO
- Typical power consumption: 65 mA for 4-output channel, 23 mA for 1-output channel.
- Universal clock input, two reference inputs for redundancy
- Differential AC-coupled or LVCMOS: 10 MHz to 200 MHz
- Crystal: 10 MHz to 50 MHz
- Flexible output clock distribution
- 4 channel dividers: Up to 5 unique output frequencies from 24 kHz to 328.125 MHz
- Combination of LVDS-like, LP-HCSL or LVCMOS outputs on OUT0 – OUT4 pins
- Glitchless output divider switching and output channel synchronization
- Individual output enable through GPIO and register
- Frequency margining options
- DCO mode: frequency increment/decrement with 10ppb or less step-size
- Fully-integrated, configurable loop bandwidth: 100 kHz to 1.6 MHz
- Single or mixed supply for level translation: 1.8 V/2.5 V/3.3 V
- Configurable GPIOs and flexible configuration options
- I2C-compatible interface: up to 400 kHz
- Integrated EEPROM with two pages and external select pin. In-situ programming allowed.
- Supports 100-Ω systems
- Low electromagnetic emissions
- Small footprint: 24-pin VQFN (4 mm × 4 mm)
The CDCE6214 is a four-channel, ultra-low power, medium grade jitter, clock generator that can generate five independent clock outputs selectable between various modes of drivers. The input source could be a single-ended or differential input clock source, or a crystal. The CDCE6214 features a frac-N PLL to synthesize unrelated base frequency from any input frequency. The CDCE6214 can be configured through the I2C interface. In the absence of the serial interface, the GPIO pins can be used in Pin Mode to configure the product into distinctive configurations.
On-chip EEPROM can be used to change the configuration, which is pre-selectable through the pins. The device provides frequency margining options with glitch-free operation to support system design verification tests (DVT) and Ethernet Audio-Video Bridging (eAVB). Fine frequency margining is available on any output channel by steering the fractional feedback divider in DCO mode.
Internal power conditioning provides excellent power supply ripple rejection (PSRR), reducing the cost and complexity of the power delivery network. The analog and digital core blocks operate from either a 1.8-V, 2.5-V, or 3.3-V ±5% supply, and output blocks operate from a 1.8-V, 2.5-V, or 3.3-V ±5% supply.
The CDCE6214 enables high-performance clock trees from a single reference at ultra-low power with a small footprint. The factory- and user-programmable EEPROM features make the CDCE6214 an easy-to-use, instant-on clocking device with a low power consumption.
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技術文件
| 類型 | 標題 | 日期 | ||
|---|---|---|---|---|
| * | Data sheet | CDCE6214 Ultra-Low Power Clock Generator With One PLL, Four Differential Outputs, Two Inputs, and Internal EEPROM datasheet | PDF | HTML | 2020年 7月 2日 |
| Application note | Clocking for PCIe Applications | PDF | HTML | 2023年 11月 28日 | |
| User guide | CDCE6214-Q1 Registers (Rev. B) | 2019年 11月 27日 |
設計與開發
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CDCE6214-Q1EVM — 4 個差分和 1 個 LVCMOS 輸出時脈產生器評估模組
評估模組提供 USB 介面，可存取 I2C 匯流排以與 CDCE6214-Q1 通訊。接腳控制模式可將裝置設定為特定的操作模式。
CLOCK-TREE-ARCHITECT — 時鐘樹架構程式設計軟體
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PSpice for TI 設計和模擬環境可讓您使用其內建函式庫來模擬複雜的混合訊號設計。在進行佈局和製造之前，建立完整的終端設備設計和解決方案原型，進而縮短上市時間並降低開發成本。
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| 封裝 | 針腳 | CAD 符號、佔位空間與 3D 模型 |
|---|---|---|
| VQFN (RGE) | 24 | Ultra Librarian |
訂購與品質
- RoHS
- REACH
- 產品標記
- 鉛塗層/球物料
- MSL 等級/回焊峰值
- MTBF/FIT 估算值
- 材料內容
- 認證摘要
- 進行中持續性的可靠性監測
- 晶圓廠位置
- 組裝地點
建議產品可能具有與此 TI 產品相關的參數、評估模組或參考設計。