CDCE6214-Q1
- AEC-Q100 qualified for automotive applications
- Temperature grade 2: –40°C to 105°C
- Functional Safety-Capable
- Configurable high performance, low-power, frac-N
PLL with RMS jitter with spurs (12kHz – 20MHz,
Fout > 100MHz) as:
- Integer mode:
- Differential output: 350fs typical (typ.), 600fs maximum (max)
- LVCMOS output: 1.05ps typ., 1.5ps max
- Fractional mode:
- Differential output: 1.7ps typ., 2.1ps max
- LVCMOS output: 2.0ps typ., 4.0ps max
- Integer mode:
- Supports PCIe Gen1/2/3/4 with SSC and Gen 1/2/3/4/5/6 without SSC
- Typ. power consumption: 65mA for 4-output channel, 23mA for 1-output channel.
- Universal clock input
- Differential AC-coupled or LVCMOS: 10MHz to 200MHz
- Crystal: 10MHz to 50MHz
- Flexible output clock distribution
- Four channel dividers: Up to five unique output frequencies from 24kHz to 328.125MHz
- Combination of LVDS-like, LP-HCSL or LVCMOS outputs on OUT0 – OUT4 pins
- Glitchless output divider switching and output channel synchronization
- Individual output enable through GPIO and register
- Frequency margining options
- DCO mode: frequency increment/decrement with 10ppb or less step-size
- Fully-integrated, configurable loop bandwidth: 100kHz to 1.6MHz
- Single or mixed supply for level translation: 1.8V, 2.5V, 3.3V
- Configurable GPIOs and flexible configuration options
- I2C-compatible interface: up to 400kHz
- Integrated EEPROM with two pages and external select pin. In-situ programming allowed.
- Supports 100Ω systems
- Low electromagnetic emissions
- Small footprint: 24-pin VQFN (4mm × 4mm)
The CDCE6214-Q1 is a 4-channel, ultra-low power, medium grade jitter, clock generator for automotive application that can generate five independent clock outputs selectable between various modes of drivers. The input source can be a single-ended or differential input clock source, or a crystal. The CDCE6214-Q1 features a frac-N PLL to synthesize unrelated base frequency from any input frequency.
The CDCE6214-Q1 can be configured through the I2C interface in fall-back mode only. In the absence of the serial interface, the GPIO pins can be used in pin mode to configure the product into distinctive configurations.
On-chip EEPROM can be used to change the configuration, which is pre-selectable through the pins. The device provides frequency margining options with glitch-free operation to support system design verification tests (DVT) and Ethernet Audio-Video Bridging (eAVB). Fine frequency margining is available on any output channel by steering the fractional feedback divider in DCO mode.
Internal power conditioning provides excellent power supply ripple rejection (PSRR), reducing the cost and complexity of the power delivery network. The analog and digital core blocks operate from either a 1.8V, 2.5V, or 3.3V ±5% supply, and output blocks operate from a 1.8V, 2.5V, or 3.3V ±5% supply.
The CDCE6214-Q1 enables high-performance clock trees from a single reference at ultra-low power with a small footprint. The factory- and user-programmable EEPROM features make the CDCE6214-Q1 an easy-to-use, instant on clocking device with a low power consumption.
技術文件
| 重要文件 | 類型 | 標題 | 格式選項 | 下載最新的英文版本 | 日期 | |
|---|---|---|---|---|---|---|
| * | 資料表 | CDCE6214-Q1 Ultra-Low Power Clock Generator With One PLL, Four Differential Outputs, Two Inputs, and Internal EEPROM datasheet (Rev. C) | PDF | HTML | 2025/7/31 | ||
| 應用說明 | Clocking for PCIe Applications | PDF | HTML | 2023/11/28 | |||
| 功能安全資訊 | CDCE6214-Q1 Functional Safety, FIT Rate, Failure Mode Distribution and Pin FMA | PDF | HTML | 2021/4/15 | |||
| 技術文章 | Optimizing eAVB for automotive applications using clock generators | PDF | HTML | 2020/5/8 | |||
| 證書 | CDCE6214-Q1EVM Declaration of Conformity (DoC) | 2020/4/28 | ||||
| 應用說明 | Frequency Margining and eAVB System Design With CDCE6214-Q1 | PDF | HTML | 2020/4/2 | |||
| 應用說明 | CDCE6214-Q1 Crystal-Based Oscillator Design | 2019/12/9 | ||||
| 使用指南 | CDCE6214-Q1 Registers (Rev. B) | 2019/11/27 |
設計與開發
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CDCE6214-Q1EVM — 4 個差分和 1 個 LVCMOS 輸出時脈產生器評估模組
評估模組提供 USB 介面，可存取 I2C 匯流排以與 CDCE6214-Q1 通訊。接腳控制模式可將裝置設定為特定的操作模式。
TICSPRO-SW — TICS Pro GUI and Live Programming Tool for Clocking Devices
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| 封裝 | 針腳 | CAD 符號、佔位空間與 3D 模型 |
|---|---|---|
| VQFN (RGE) | 24 | Ultra Librarian |
訂購與品質
建議產品可能具有與此 TI 產品相關的參數、評估模組或參考設計。