產品詳細資料

Number of outputs 9 Output type LVCMOS Output frequency (max) (MHz) 230 Core supply voltage (V) 1.8 Output supply voltage (V) 2.5, 3.3 Input type LVCMOS, XTAL Operating temperature range (°C) -40 to 85 Features Integrated EEPROM, Multiplier or divider, Spread-spectrum clocking (SSC) Rating Catalog
Number of outputs 9 Output type LVCMOS Output frequency (max) (MHz) 230 Core supply voltage (V) 1.8 Output supply voltage (V) 2.5, 3.3 Input type LVCMOS, XTAL Operating temperature range (°C) -40 to 85 Features Integrated EEPROM, Multiplier or divider, Spread-spectrum clocking (SSC) Rating Catalog
TSSOP (PW) 24 49.92 mm² (7.8 mm × 6.4 mm)
  • Member of programmable clock generator family
    • CDCEx913: 1 PLL, 3 outputs
    • CDCEx925: 2 PLLs, 5 outputs
    • CDCEx937: 3 PLLs, 7 outputs
    • CDCEx949: 4 PLLs, 9 outputs
  • In-system programmability and EEPROM
    • Serial programmable volatile register
    • Nonvolatile EEPROM to store customer settings
  • Flexible input clocking concept
    • External crystal: 8MHz to 32MHz
    • On-chip VCXO pull-range: ±150ppm
    • Single-ended LVCMOS up to 160MHz
  • Free selectable output frequency up to 230MHz
  • Low-noise PLL core
    • PLL loop filter components integrated
    • Low period jitter: 60ps (typical)
  • Separate output supply pins
    • CDCE949: 3.3V and 2.5V
    • CDCEL949: 1.8V
  • Flexible clock driver
    • Three user-definable control inputs [S0/S1/S2] (for example: SSC selection, frequency switching, output enable or power down)
    • Generates highly accurate clocks for video, audio, USB, IEEE1394, RFID, Bluetooth, WLAN, Ethernet™, and GPS
    • Generates common clock frequencies used with TI-DaVinci™, OMAP™, DSPs
    • Programmable SSC modulation
    • Enables 0ppm clock generation
  • 1.8V device core supply
  • Wide temperature range: –40°C to 85°C
  • Packaged in TSSOP
  • Development and programming kit for easy PLL design and programming (TI Pro-Clock™)
  • Member of programmable clock generator family
    • CDCEx913: 1 PLL, 3 outputs
    • CDCEx925: 2 PLLs, 5 outputs
    • CDCEx937: 3 PLLs, 7 outputs
    • CDCEx949: 4 PLLs, 9 outputs
  • In-system programmability and EEPROM
    • Serial programmable volatile register
    • Nonvolatile EEPROM to store customer settings
  • Flexible input clocking concept
    • External crystal: 8MHz to 32MHz
    • On-chip VCXO pull-range: ±150ppm
    • Single-ended LVCMOS up to 160MHz
  • Free selectable output frequency up to 230MHz
  • Low-noise PLL core
    • PLL loop filter components integrated
    • Low period jitter: 60ps (typical)
  • Separate output supply pins
    • CDCE949: 3.3V and 2.5V
    • CDCEL949: 1.8V
  • Flexible clock driver
    • Three user-definable control inputs [S0/S1/S2] (for example: SSC selection, frequency switching, output enable or power down)
    • Generates highly accurate clocks for video, audio, USB, IEEE1394, RFID, Bluetooth, WLAN, Ethernet™, and GPS
    • Generates common clock frequencies used with TI-DaVinci™, OMAP™, DSPs
    • Programmable SSC modulation
    • Enables 0ppm clock generation
  • 1.8V device core supply
  • Wide temperature range: –40°C to 85°C
  • Packaged in TSSOP
  • Development and programming kit for easy PLL design and programming (TI Pro-Clock™)

The CDCE949 and CDCEL949 are modular PLL-based low cost, high-performance, programmable clock synthesizers, multipliers, and dividers. These devices generate up to nine output clocks from a single input frequency. Each output is programmable in-system for any clock frequency up to 230MHz, using up to four independent configurable PLLs.

The CDCEx949 has separate output supply pins (VDDOUT): 1.8V for the CDCEL949 and 2.5V to 3.3V for the CDCE949.

The input accepts an external crystal or LVCMOS clock signal. If an external crystal is used, an on-chip load capacitor is adequate for most applications. The value of the load capacitor is programmable from 0pF to 20pF. Additionally, an on-chip VCXO is selectable, allowing synchronization of the output frequency to an external control signal, that is, a PWM signal.

The deep M/N divider ratio allows the generation of 0ppm audio or video, networking (WLAN, Bluetooth, Ethernet, GPS) or Interface (USB, IEEE1394, Memory Stick) clocks from a reference input frequency, such as 27MHz.

All PLLs support spread spectrum clocking (SSC). SSC can be center-spread or down-spread clocking. This is a common technique to reduce electromagnetic interference (EMI).

Based on the PLL frequency and the divider settings, the internal loop-filter components are automatically adjusted to achieve high stability, and to optimize the jitter-transfer characteristics of each PLL.

The device supports non-volatile EEPROM programming for easy customization of the device to the application. The CDCEx949 is preset to a factory-default configuration. The device can be reprogrammed to a different application configuration before PCB assembly, or reprogrammed by in-system programming. All device settings are programmable through the SDA and SCL bus, a 2-wire serial interface.

The CDCE949 and CDCEL949 are modular PLL-based low cost, high-performance, programmable clock synthesizers, multipliers, and dividers. These devices generate up to nine output clocks from a single input frequency. Each output is programmable in-system for any clock frequency up to 230MHz, using up to four independent configurable PLLs.

The CDCEx949 has separate output supply pins (VDDOUT): 1.8V for the CDCEL949 and 2.5V to 3.3V for the CDCE949.

The input accepts an external crystal or LVCMOS clock signal. If an external crystal is used, an on-chip load capacitor is adequate for most applications. The value of the load capacitor is programmable from 0pF to 20pF. Additionally, an on-chip VCXO is selectable, allowing synchronization of the output frequency to an external control signal, that is, a PWM signal.

The deep M/N divider ratio allows the generation of 0ppm audio or video, networking (WLAN, Bluetooth, Ethernet, GPS) or Interface (USB, IEEE1394, Memory Stick) clocks from a reference input frequency, such as 27MHz.

All PLLs support spread spectrum clocking (SSC). SSC can be center-spread or down-spread clocking. This is a common technique to reduce electromagnetic interference (EMI).

Based on the PLL frequency and the divider settings, the internal loop-filter components are automatically adjusted to achieve high stability, and to optimize the jitter-transfer characteristics of each PLL.

The device supports non-volatile EEPROM programming for easy customization of the device to the application. The CDCEx949 is preset to a factory-default configuration. The device can be reprogrammed to a different application configuration before PCB assembly, or reprogrammed by in-system programming. All device settings are programmable through the SDA and SCL bus, a 2-wire serial interface.

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開發板

CDCE949PERF-EVM — CDCE949 性能評估模組

The CDCE949Perf-Evaluation Module will help to verify the functionality and performance of CDCE949 with the options of crystal and 1.8 V LVCMOS inputs. The outputs can be connected to the Oscilloscope directly with SMA cables. The below information/items can be included The EVM use’s (...)

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開發板

CDCEL9XXPROGEVM — CDCE(L)949 系列 EEPROM 程式設計基板

The clock generator CDCE(L)949 family has integrated EEPROM that allows the default frequency settings to be saved upon start up. CDCEL9XXPROGEVM is a programming board that allows a fast programming of prototyping samples or small production quantities. It applies to all 8 devices in the family: (...)

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應用軟體及架構

SCAC097 — Executable File Without LabVIEW 8.2 Run Time Engine

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驅動程式或資料庫

SCAC131 — Drivers for the CDCEL9xx programmer EVM

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支援軟體

CLOCKPRO — ClockPro Software

TI's ClockPro software allows users to program/configure the following devices in a friendly GUI interface:

  • CDCE949
  • CDCE937
  • CDCE925
  • CDCE913
  • CDCE906
  • CDCE706
  • CDCEL949
  • CDCEL937
  • CDCEL925
  • CDCEL913

It is intended to be used with the evaluation modules of the above devices.

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SCAC073 — TI-Pro-Clock Programming Software

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模擬型號

CDCE949 IBIS Model (Rev. B)

SCAC094B.ZIP (42 KB) - IBIS 模型
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設計工具

CLOCK-TREE-ARCHITECT — 時鐘樹架構程式設計軟體

時鐘樹架構是一款時鐘樹合成工具,可根據您的系統需求產生時鐘樹解決方案,進而簡化您的設計流程。此工具可從廣泛的計時產品資料庫中汲取資料,產生系統級多晶片計時解決方案。

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參考設計

TIDA-010057 — 超音波智慧探測器電源供應參考設計

醫學影像的顯著技術進步與高度整合,特別是手持式超音波智慧探測器,推進工程師開發出體積小巧且高效率、抗雜訊抗擾的電源解決方案。此參考設計記錄了我們具有 TX7332 傳送晶片和 AFE5832LP 接收晶片的高性能 128 通道 Tx/64 通道 Rx 超音波智慧探測器解決方案的端對端電源和資料解決方案。電源樹狀結構包括用於傳送的單級無變壓器 HV 產生(高達 +/- 80 V 且高度 <5 mm),以及來自 5V USB Type-C™ 輸入的 AFE 和 FPGA 負載點 LV。此設計可實現低雜訊(<10mV 漣波)高效電源軌,以及更出色的熱性能(溫度上升 < 10°C),實現系統效率提升 ~80%,接收資料 SNR >55dB,以及超精巧尺寸 (90mm x 45mm x 20mm)。所有電源軌皆可使用我們的整合式緩衝分壓器 CDCE949 與外部時脈同步。此設計也支援 1S 電池輸入,正常超音波運作可長達 2 小時。
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參考設計

TIDA-010269 — 手持式超音波成像裝置電源供應參考設計

此參考設計專為強化採用新一代發射器與接收器的新一代 128 通道超音波智慧探測器而打造。尺寸精巧 (80mm × 45mm × 20mm),包含所有 128 通道智慧探測器的電源功能,且效率高於 80%。這款無變壓器高電壓電源供應器(25mA 時為 ±75V)是全新升壓穩壓器,可讓參考設計符合大多數智慧探測器應用。
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封裝 針腳 CAD 符號、佔位空間與 3D 模型
TSSOP (PW) 24 Ultra Librarian

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