CDCLVD2102

現行

低抖動雙路 1:2 通用 LVDS 緩衝器

立即訂購

產品規格表

document-pdfAcrobat Dual 1:2 Low Additive Jitter LVDS Buffer datasheet (Rev. A) (英文)

CDCLVD2102

現行

產品規格表

立即訂購

產品詳細資料

Number of outputs

4

Additive RMS jitter (typ) (fs)

171

Core supply voltage (V)

2.5

Output supply voltage (V)

2.5

Output skew (ps)

15

Operating temperature range (°C)

-40 to 85

Rating

Catalog

Output type

LVDS

Input type

LVCMOS, LVDS, LVPECL

Number of outputs

4

Additive RMS jitter (typ) (fs)

171

Core supply voltage (V)

2.5

Output supply voltage (V)

2.5

Output skew (ps)

15

Operating temperature range (°C)

-40 to 85

Rating

Catalog

Output type

LVDS

Input type

LVCMOS, LVDS, LVPECL

VQFN (RGT)

16

9 mm² (3 mm × 3 mm)

Dual 1:2 Differential Buffer
Low Additive Jitter <300 fs RMS in 10-kHz to 20-MHz
Low Within Bank Output Skew of 15 ps (Max)
Universal Inputs Accept LVDS, LVPECL, LVCMOS
One Input Dedicated for Two Outputs
Total of 4 LVDS Outputs, ANSI EIA/TIA-644A Standard Compatible
Clock Frequency up to 800 MHz
2.375–2.625V Device Power Supply
LVDS Reference Voltage, V_{AC_REF}, Available for Capacitive Coupled Inputs
Industrial Temperature Range –40°C to 85°C
Packaged in 3mm × 3mm 16-Pin QFN (RGT)
ESD Protection Exceeds 3 kV HBM, 1 kV CDM
APPLICATIONS
- Telecommunications/Networking
- Medical Imaging
- Test and Measurement Equipment
- Wireless Communications
- General Purpose Clocking

Dual 1:2 Differential Buffer
Low Additive Jitter <300 fs RMS in 10-kHz to 20-MHz
Low Within Bank Output Skew of 15 ps (Max)
Universal Inputs Accept LVDS, LVPECL, LVCMOS
One Input Dedicated for Two Outputs
Total of 4 LVDS Outputs, ANSI EIA/TIA-644A Standard Compatible
Clock Frequency up to 800 MHz
2.375–2.625V Device Power Supply
LVDS Reference Voltage, V_{AC_REF}, Available for Capacitive Coupled Inputs
Industrial Temperature Range –40°C to 85°C
Packaged in 3mm × 3mm 16-Pin QFN (RGT)
ESD Protection Exceeds 3 kV HBM, 1 kV CDM
APPLICATIONS
- Telecommunications/Networking
- Medical Imaging
- Test and Measurement Equipment
- Wireless Communications
- General Purpose Clocking

The CDCLVD2102 clock buffer distributes two clock inputs (IN0, IN1) to a total of 4 pairs of differential LVDS clock outputs (OUT0, OUT3). Each buffer block consists of one input and 2 LVDS outputs. The inputs can either be LVDS, LVPECL, or LVCMOS.

The CDCLVD2102 is specifically designed for driving 50- transmission lines. If driving the inputs in single ended mode, the appropriate bias voltage (V_{AC_REF}) should be applied to the unused negative input pin.

Using the control pin (EN), outputs can be either disabled or enabled. If the EN pin is left open two buffers with all outputs are enabled, if switched to a logical "0" both buffers with all outputs are disabled (static logical "0"), if switched to a logical "1", one buffer with two outputs is disabled and another buffer with two outputs is enabled. The part supports a fail safe function. It incorporates an input hysteresis, which prevents random oscillation of the outputs in absence of an input signal.

The device operates in 2.5V supply environment and is characterized from –40°C to 85°C (ambient temperature). The CDCLVD2102 is packaged in small 16-pin, 3-mm × 3-mm QFN package.

The CDCLVD2102 clock buffer distributes two clock inputs (IN0, IN1) to a total of 4 pairs of differential LVDS clock outputs (OUT0, OUT3). Each buffer block consists of one input and 2 LVDS outputs. The inputs can either be LVDS, LVPECL, or LVCMOS.

The CDCLVD2102 is specifically designed for driving 50- transmission lines. If driving the inputs in single ended mode, the appropriate bias voltage (V_{AC_REF}) should be applied to the unused negative input pin.

Using the control pin (EN), outputs can be either disabled or enabled. If the EN pin is left open two buffers with all outputs are enabled, if switched to a logical "0" both buffers with all outputs are disabled (static logical "0"), if switched to a logical "1", one buffer with two outputs is disabled and another buffer with two outputs is enabled. The part supports a fail safe function. It incorporates an input hysteresis, which prevents random oscillation of the outputs in absence of an input signal.

The device operates in 2.5V supply environment and is characterized from –40°C to 85°C (ambient temperature). The CDCLVD2102 is packaged in small 16-pin, 3-mm × 3-mm QFN package.

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重要文件	類型	標題	格式選項	下載最新的英文版本		日期
*	資料表	Dual 1:2 Low Additive Jitter LVDS Buffer datasheet (Rev. A)				2010/6/15
	使用指南	Low-Additive Jitter, Four LVDS Outputs Clock Buffer Evaluation Board				2010/6/14

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模擬型號

CDCLVD2102 IBIS Model (Rev. B)

SLLM093B.ZIP (14 KB) - IBIS 模型

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CDCLVD2102

低抖動雙路 1:2 通用 LVDS 緩衝器

CDCLVD2102

產品詳細資料

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技術文件

設計與開發

CDCLVD2102 IBIS Model (Rev. B)

CLOCK-TREE-ARCHITECT — 時鐘樹架構程式設計軟體

PLLATINUMSIM-SW — PLL 迴路濾波器、相位雜訊、鎖定時間與雜散模擬工具

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