DS25CP104A
- DC - 3.125 Gbps Low Jitter, Low Skew, Low Power Operation
- Pin and SMBus Configurable, Fully Differential, Non-Blocking Architecture
- Pin (Two Levels) and SMBus (Four Levels) Selectable Pre-Emphasis and Equalization Eliminate ISI Jitter
- Wide Input Common Mode Range Enables Easy Interface to CML and LVPECL Drivers
- LOS Circuitry Detects Open Inputs Fault Condition
- On-Chip 100Ω Input and Output Termination Minimizes Insertion and Return Losses, Reduces Component Count, Minimizes Board Space The DS25CP114 Eliminates the On-Chip Input Termination for Added Design Flexibility.
- 8 kV ESD on LVDS I/O Pins Protects Adjoining Components
- Small 6 mm x 6 mm WQFN-40 Space Saving Package
All trademarks are the property of their respective owners.
沒有此產品的詳細資訊。
技術文件
找不到結果。請清除您的搜尋條件，然後再試一次。
檢視所有 7
| 重要文件 | 類型 | 標題 | 格式選項 | 下載最新的英文版本 | 日期 | |
|---|---|---|---|---|---|---|
| * | 資料表 | DS25CP104A/CP114 3.125 Gbps 4x4 LVDS Xpoint Sw w/Xmit Pre-Emp & Receive Equal datasheet (Rev. C) | 2013/3/4 | |||
| 選擇指南 | Broadcast and Professional Video Interface Solutions (Rev. E) | PDF | HTML | 2017/4/5 | |||
| 應用說明 | LVDS Repeaters and Crosspoints Extend the Reach of FPD-Link II Interfaces (Rev. A) | 2013/4/29 | ||||
| 應用說明 | AN-1957 LVDS Signal Conditioners Reduce Data-Dependent Jitter (Rev. A) | 2013/4/26 | ||||
| 應用說明 | Triple Rate SDI IP FPGA Resource Utilization on SDXILEVK/AES-EXP-SDI-G Ref Dsgn (Rev. A) | 2013/4/26 | ||||
| 應用說明 | DS25CP104 in 3G SDI Router Application | 2008/8/20 | ||||
| 應用說明 | A 3 Gbps SDI Connectivity Solution Supporting Uncompressed 1080p60 Video | 2008/3/18 |
設計與開發
如需其他條款或必要資源，請按一下下方的任何標題以檢視詳細頁面 (如有)。
| 封裝 | 針腳 | CAD 符號、佔位空間與 3D 模型 |
|---|---|---|
| WQFN (RTA) | 40 | Ultra Librarian |
訂購與品質
建議產品可能具有與此 TI 產品相關的參數、評估模組或參考設計。