DS320PR1601
- 16-lane linear redriver supporting PCIe 5.0, CXL 2.0, CCIX , and UPI 2.0
- Supports data rates up to 32-Gbps
- Intel retimer common footprint compatible
- 64 integrated AC coupling capacitors on Tx pins inside package saving board space
- CTLE boosts of 21 dB at 16 GHz
- Ultra-low latency of 130 ps
- Low additive random jitter of 50 fs for PRBS data
- Single 3.3 V supply
- Low active power of 164 mW/channel
- I 2C/SMBus or EEPROM programming
- Automatic receiver detection for PCIe use cases
- Seamless support for PCIe link training
- Internal voltage regulator provides immunity to supply noise
- Support for x4, x8, x16 bus width
- 8.90 mm × 22.80 mm BGA package
The DS320PR1601 is a 32-channel (16-channel in each direction) or x16 (16-lane) low-power high-performance linear repeater or redriver designed to support PCIe 5.0, CXL 2.0, UPI 2.0 and other interfaces up to 32 Gbps.
The DS320PR1601 receivers deploy continuous time linear equalizers (CTLE) to provide a programmable high-frequency boost. The equalizer can open an input eye that is completely closed due to inter-symbol interference (ISI) induced by an interconnect medium, such as PCB traces. The CTLE receiver is followed by a linear output driver. The linear datapaths of DS320PR1601 preserves transmit preset signal characteristics. The linear redriver becomes part of the passive channel that as a whole get link trained for best transmit and receive equalization settings. This transparency in the link training protocol results in best electrical link and lowest possible latency. Low channel-channel cross-talk, low additive jitter and excellent return loss makes the device almost a passive element in the link, but with its equalization.
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技術文件
| 重要文件 | 類型 | 標題 | 格式選項 | 下載最新的英文版本 | 日期 | |
|---|---|---|---|---|---|---|
| * | 資料表 | DS320PR1601 32 Gbps 16 Lane PCIe 5.0, CXL 2.0 Linear Redriver datasheet | PDF | HTML | 2023/6/22 | ||
| 應用說明 | How to Tune TI PCIe Gen5 Redrivers (Rev. B) | PDF | HTML | 2026/1/9 | |||
| 應用說明 | Understanding TI PCIe Redriver Equalization | PDF | HTML | 2024/7/2 | |||
| 應用說明 | Eye Scan With TI PCI-Express Gen5.0 Redrivers (Rev. A) | PDF | HTML | 2024/1/16 | |||
| 應用說明 | High-Speed PCB Layout for PCIe Gen 5 | PDF | HTML | 2023/6/20 | |||
| 使用指南 | DS160PR1601 and DS320PR1601 Programming Guide (Rev. A) | PDF | HTML | 2023/6/20 | |||
| 證書 | DS320PR1601RSC-EVM EU Declaration of Conformity (DoC) | 2021/4/23 |
設計與開發
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DS320PR1601RSCEVM — DS320PR1601 32 通道 PCIe® 5.0 線性轉接驅動器評估模組
SIGCONARCHITECT3 — Texas Instruments SigCon Architect EVM GUI v3.0.0.14 Setup
SIGCONARCHITECT3-WRTE — Texas Instruments SigCon Architect EVM GUI v3 Setup with RTE
| 封裝 | 針腳 | CAD 符號、佔位空間與 3D 模型 |
|---|---|---|
| NFBGA (ZDG) | 354 | Ultra Librarian |
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