DS32EL0124
- 5-bit DDR LVDS Parallel Data Interface
- Programmable Receive Equalization
- Selectable DC-Balance Decoder
- Selectable De-Scrambler
- Remote Sense for Automatic Detection and Negotiation of Link Status
- No External Receiver Reference Clock Required
- LVDS Parallel Interface
- Programmable LVDS Output Clock Delay
- Supports Output Data-Valid Signaling
- Supports Keep-Alive Clock Output
- On Chip LC VCOs
- Redundant Serial Input (ELX device only)
- Retimed Serial Output (ELX device only)
- Configurable PLL Loop Bandwidth
- Configurable via SMBus
- Loss of Lock and Error Reporting
- 48-pin WQFN Package with Exposed DAP
Key Specifications
- 1.25 to 3.125 Gbps Serial Data Rate
- 125 to 312.5 MHz DDR Parallel Clock
- -40° to +85°C Temperature Range
- > 8 kV ESD (HBM) Protection
- 0.5 UI Minimum Input Jitter Tolerance (1.25 Gbps)
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The DS32EL0124/DS32ELX0124 integrates clock and data recovery modules for high-speed serial communication over FR-4 printed circuit board backplanes, balanced cables, and optical fiber. This easy-to-use chipset integrates advanced signal and clock conditioning functions, with an FPGA friendly interface.
The DS32EL0124/DS32ELX0124 deserializes up to 3.125 Gbps of high speed serial data to 5 LVDS outputs without the need for an external reference clock. With DC-balance decoding enabled, the application payload of 2.5 Gbps is deserialized to 4 LVDS outputs.
The DS32EL0124/DS32ELX01214 deserializers feature a remote sense capability to automatically signal link status conditions to its companion DS32EL0421/ELX0421 serializers without requiring an additional feedback path.
The parallel LVDS interface of these devices reduce FPGA I/O pins, board trace count and alleviates EMI issues, when compared to traditional single-ended wide bus interfaces.
The DS32EL0124/ELX0124 is programmable through a SMBus interface as well as through control pins.
技術文件
| 重要文件 | 類型 | 標題 | 格式選項 | 下載最新的英文版本 | 日期 | |
|---|---|---|---|---|---|---|
| * | 資料表 | DS32EL0124/ELX0124 125MHz-312.5MHz FPGA-Link Deserializr w/DDR LVDS Para I/F datasheet (Rev. K) | 2013/4/15 | |||
| 應用說明 | LVDS Timing DS32ELX0421 and DS32ELX0124 Serializers and Deserializers (Rev. A) | 2013/4/26 | ||||
| 應用說明 | Expanding the Payload w/FPGA-Link DS32ELX0421 and DS32ELX0124 SER/DES (Rev. A) | 2013/4/26 |
設計與開發
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| 封裝 | 針腳 | CAD 符號、佔位空間與 3D 模型 |
|---|---|---|
| WQFN (RHS) | 48 | Ultra Librarian |
訂購與品質
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