DS90C031B
- >155.5 Mbps (77.7 MHz) switching rates
- High impedance LVDS outputs with power-off
- ±350 mV differential signaling
- Ultra low power dissipation
- 400 ps maximum differential skew (5V, 25°C)
- 3.5 ns maximum propagation delay
- Industrial operating temperature range
- Pin compatible with DS26C31, MB571 (PECL) and 41LG (PECL)
- Conforms to ANSI/TIA/EIA-644 LVDS standard
- Offered in narrow body SOIC package
- Fail-safe logic for floating inputs
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The DS90C031B is a quad CMOS differential line driver designed for applications requiring ultra low power dissipation and high data rates. The device supports data rates in excess of 155.5 Mbps (77.7 MHz) and uses Low Voltage Differential Signaling (LVDS) technology.
The DS90C031B accepts TTL/CMOS input levels and translates them to low voltage (350 mV) differential output signals. In addition the driver supports a TRI-STATE function that may be used to disable the output stage, disabling the load current, and thus dropping the device to an ultra low idle power state of 11 mW typical.
In addition, the DS90C031B provides power-off high impedance LVDS outputs. This feature assures minimal loading effect on the LVDS bus lines when VCC is not present.
The DS90C031B and companion line receiver (DS90C032B) provide a new alternative to high power pseudo‐ECL devices for high speed point-to-point interface applications.
技術文件
| 類型 | 標題 | 日期 | ||
|---|---|---|---|---|
| * | Data sheet | DS90C031B LVDS Quad CMOS Differential Line Driver datasheet (Rev. B) | 2013年 3月 4日 | |
| Application brief | How Far, How Fast Can You Operate LVDS Drivers and Receivers? | 2018年 8月 3日 | ||
| Application brief | How to Terminate LVDS Connections with DC and AC Coupling | 2018年 5月 16日 | ||
| Application note | AN-1110 LVDS Quad Dynamic I CC vs Frequency | 2004年 5月 15日 | ||
| Application note | An Overview of LVDS Technology | 1998年 10月 5日 |
設計與開發
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| 封裝 | 引腳 | 下載 |
|---|---|---|
| SOIC (D) | 16 | 檢視選項 |
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