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DS90CF383

不推薦在新設計中採用

3.3-V LVDS 24 位元平板顯示器 (FPD-Link) - 65 MHz

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DS90CF383

不推薦在新設計中採用
產品規格表 立即訂購

產品詳細資料

Applications In-vehicle Infotainment (IVI) Features Low-EMI Point-to-Point Communication EMI reduction LVDS Rating Catalog Operating temperature range (°C) to
Applications In-vehicle Infotainment (IVI) Features Low-EMI Point-to-Point Communication EMI reduction LVDS Rating Catalog Operating temperature range (°C) to
TSSOP (DGG) 56 113.4 mm² (14 mm × 8.1 mm)
  • 20 to 65 MHz shift clock support
  • Single 3.3V supply
  • Chipset (Tx + Rx) power consumption < 250 mW (typ)
  • Power-down mode (< 0.5 mW total)
  • Single pixel per clock XGA (1024×768) ready
  • Supports VGA, SVGA, XGA and higher addressability.
  • Up to 227 Megabytes/sec bandwidth
  • Up to 1.8 Gbps throughput
  • Narrow bus reduces cable size and cost
  • 290 mV swing LVDS devices for low EMI
  • PLL requires no external components
  • Low profile 56-lead TSSOP package
  • Falling edge data strobe Transmitter
  • Compatible with TIA/EIA-644 LVDS standard
  • ESD rating > 7 kV
  • Operating Temperature: -40°C to +85°C

TRI-STATE® is a registered trademark of National Semiconductor Corporation.
  • 20 to 65 MHz shift clock support
  • Single 3.3V supply
  • Chipset (Tx + Rx) power consumption < 250 mW (typ)
  • Power-down mode (< 0.5 mW total)
  • Single pixel per clock XGA (1024×768) ready
  • Supports VGA, SVGA, XGA and higher addressability.
  • Up to 227 Megabytes/sec bandwidth
  • Up to 1.8 Gbps throughput
  • Narrow bus reduces cable size and cost
  • 290 mV swing LVDS devices for low EMI
  • PLL requires no external components
  • Low profile 56-lead TSSOP package
  • Falling edge data strobe Transmitter
  • Compatible with TIA/EIA-644 LVDS standard
  • ESD rating > 7 kV
  • Operating Temperature: -40°C to +85°C

TRI-STATE® is a registered trademark of National Semiconductor Corporation.

The DS90CF383 transmitter converts 28 bits of CMOS/TTL data into four LVDS (Low Voltage Differential Signaling) data streams. A phase-locked transmit clock is transmitted in parallel with the data streams over a fifth LVDS link. Every cycle of the transmit clock 28 bits of input data are sampled and transmitted. At a transmit clock frequency of 65 MHz, 24 bits of RGB data and 3 bits of LCD timing and control data (FPLINE, FPFRAME, DRDY) are transmitted at a rate of 455 Mbps per LVDS data channel. Using a 65 MHz clock, the data throughputs is 227 Mbytes/sec.

This chipset is an ideal means to solve EMI and cable size problems associated with wide, high speed TTL interfaces.

The DS90CF383 transmitter converts 28 bits of CMOS/TTL data into four LVDS (Low Voltage Differential Signaling) data streams. A phase-locked transmit clock is transmitted in parallel with the data streams over a fifth LVDS link. Every cycle of the transmit clock 28 bits of input data are sampled and transmitted. At a transmit clock frequency of 65 MHz, 24 bits of RGB data and 3 bits of LCD timing and control data (FPLINE, FPFRAME, DRDY) are transmitted at a rate of 455 Mbps per LVDS data channel. Using a 65 MHz clock, the data throughputs is 227 Mbytes/sec.

This chipset is an ideal means to solve EMI and cable size problems associated with wide, high speed TTL interfaces.
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重要文件 類型 標題 格式選項 下載最新的英文版本 日期
* 資料表 DS90CF383 +3.3V LVDS Transmitter 24-Bit Flat Panel Display (FPD) Link-65 MHz datasheet 2004/5/13

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