DS90LV031A
- >400-Mbps (200-MHz) Switching Rates
- 0.1-ns Typical Differential Skew
- 0.4-ns Maximum Differential Skew
- 2-ns Maximum Propagation Delay
- 3.3-V Power Supply Design
- ±350-mV Differential Signaling
- Low Power Dissipation (13-mW at 3.3-V Static)
- Interoperable With Existing 5-V LVDS Devices
- Compatible With IEEE 1596.3 SCI LVDS Standard
- Compatible With TIA/EIA-644 LVDS Standard
- Industrial Operating Temperature Range
- Available in SOIC and TSSOP Surface-Mount Packaging
The DS90LV031A is a quad CMOS differential line driver designed for applications requiring ultra low power dissipation and high data rates. The device is designed to support data rates in excess of 400 Mbps (200 MHz) using Low Voltage Differential Signaling (LVDS) technology.
The DS90LV031A accepts low voltage LVTTL or LVCMOS input levels and translates them to low voltage (350 mV) differential output signals. In addition the driver supports a TRI-STATE® function that may be used to disable the output stage, disabling the load current, and thus dropping the device to an ultra low idle power state of 13 mW typical.
The EN and EN* inputs allow active Low or active High control of the TRI-STATE outputs. The enables are common to all four drivers. The DS90LV031A and companion line receiver (DS90LV032A) provide a new alternative to high power psuedo-ECL devices for high speed point-to-point interface applications.
技術文件
| 重要文件 | 類型 | 標題 | 格式選項 | 下載最新的英文版本 | 日期 | |
|---|---|---|---|---|---|---|
| * | 資料表 | DS90LV031A 3-V LVDS Quad CMOS Differential Line Driver datasheet (Rev. D) | PDF | HTML | 2016/8/25 | ||
| 應用說明 | AN-1110 LVDS Quad Dynamic I CC vs Frequency | 2004/5/15 | ||||
| 應用說明 | An Overview of LVDS Technology | 1998/10/5 |
設計與開發
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DS90LV047-48AEVM — DS90LV047-48AEVM 評估模組
| 封裝 | 針腳 | CAD 符號、佔位空間與 3D 模型 |
|---|---|---|
| SOIC (D) | 16 | Ultra Librarian |
| TSSOP (PW) | 16 | Ultra Librarian |
訂購與品質
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