DS91C180
- DC to 100+ MHz / 200+ Mbps Low Power, Low EMI Operation
- Optimal for ATCA, uTCA Clock Distribution Networks
- Meets or Exceeds TIA/EIA-899 M-LVDS Standard
- Wide Input Common Mode Voltage for Increased Noise Immunity
- DS91D180 has Type 1 Receiver Input
- DS91C180 has Type 2 Receiver Input for Fail-Safe Functionality
- Industrial Temperature Range
- Space Saving SOIC-14 Package (JEDEC MS-012)
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The DS91D180 and DS91C180 are 100 MHz M-LVDS (Multipoint Low Voltage Differential Signaling) line driver/receiver pairs designed for applications that utilize multipoint networks (e.g. clock distribution in ATCA and uTCA based systems). M-LVDS is a bus interface standard (TIA/EIA-899) optimized for multidrop networks. Controlled edge rates, tight input receiver thresholds and increased drive strength are sone of the key enhancments that make M-LVDS devices an ideal choice for distributing signals via multipoint networks.
The DS91D180/DS91C180 driver input accepts LVTTL/LVCMOS signals and converts them to differential M-LVDS signal levels. The DS91D180/DS91C180 receiver accepts low voltage differential signals (LVDS, B-LVDS, M-LVDS, LV-PECL and CML) and converts them to 3V LVCMOS signals. The DS91D180 device has a M-LVDS type 1 receiver input with no offset.The DS91C180 device has a type 2 receiver input which enable failsafe functionality.
技術文件
| 重要文件 | 類型 | 標題 | 格式選項 | 下載最新的英文版本 | 日期 | |
|---|---|---|---|---|---|---|
| * | 資料表 | DS91D180/DS91C180 100 MHz M-LVDS Line Driver/Receiver Pair datasheet (Rev. M) | 2013/4/18 | |||
| Application brief | How Far, How Fast Can You Operate MLVDS? | 2018/8/6 | ||||
| 應用說明 | Designing an ATCA Compliant M-LVDS Clock Distribution Network (Rev. B) | 2013/4/26 | ||||
| 應用說明 | Introduction to M-LVDS (TIA/EIA-899) (Rev. A) | 2013/1/3 |
設計與開發
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| 封裝 | 針腳 | CAD 符號、佔位空間與 3D 模型 |
|---|---|---|
| SOIC (D) | 14 | Ultra Librarian |