DS92LX2121
- General
- Up to 1050 Mbits/sec Data Throughput
- 10 MHz to 50 MHz Input Clock Support
- Supports 18-bit Color Depth
(RGB666 + HS, VS, DE) - Embedded Clock with DC Balanced Coding to
Support AC-Coupled Interconnects - Capable to Drive up to 10 Meters Shielded
Twisted-Pair - Bi-Directional Control Interface Channel
with I2C Support - I2C Interface for Device
Configuration. Single-Pin ID Addressing - Up to 4 GPI on DES and GPO on SER
- AT-SPEED BIST Diagnosis Feature to Validate
Link Integrity - Individual Power-Down Controls for both SER
and DES - User-Selectable Clock Edge for Parallel Data
on both SER and DES - Integrated Termination Resistors
- 1.8V- or 3.3V-Compatible Parallel Bus Interface
- Single Power Supply at 1.8V
- IEC 61000–4–2 ESD Compliant
- Temperature Range −40°C to +85°C
- DESERIALIZER — DS92LX2122
- No Reference Clock Required on Deserializer
- Programmable Receive Equalization
- LOCK Output Reporting Pin to Ensure
- EMI/EMC Mitigation
- Programmable Spread Spectrum (SSCG) Outputs
- Receiver Output Drive Strength Control (RDS)
- Receiver Staggered Outputs
The DS92LX2121/DS92LX2122 chipset offers a Channel Link III interface with a high-speed forward channel and a full-duplex control channel for data transmission over a single differential pair. The DS92LX2121/DS92LX2122 incorporates differential signaling on both the high-speed and bi-directional back channel control data paths. The Serializer/ Deserializer pair is targeted for direct connections between graphics host controller and displays modules. This chipset is ideally suited for driving video data to displays requiring 18-bit color depth (RGB666 + HS, VS, and DE) along with a bi-directional back channel control bus. The primary transport converts 21 bit data over a single high-speed serial stream, along with a separate low latency bi-directional back channel transport that accepts control information from an I2C port. Using TI’s embedded clock technology allows transparent full-duplex communication over a single differential pair, carrying asymmetrical bi-directional back channel control information in both directions. This single serial stream simplifies transferring a wide data bus over PCB traces and cable by eliminating the skew problems between parallel data and clock paths. This significantly saves system cost by narrowing data paths that in turn reduce cable width, connector size and pins.
In addition, the Deserializer provides input equalization to compensate for loss from the media over longer distances. Internal DC balanced encoding/decoding is used to support AC-Coupled interconnects.
A sleep function provides a power-savings mode when the high speed forward channel and embedded bi-directional control channel are not needed.
The Serializer is offered in a 40-pin lead in WQFN and Deserializer is offered in a 48-pin WQFN packages.
技術文件
| 重要文件 | 類型 | 標題 | 格式選項 | 下載最新的英文版本 | 日期 | |
|---|---|---|---|---|---|---|
| * | 資料表 | DS92LX2121/22 10 - 50 MHz DC-Balanced Ch Link III Bi-Directional Control SER/DES datasheet (Rev. J) | 2014/1/17 | |||
| 應用說明 | High-Speed Layout Guidelines for Reducing EMI for LVDS SerDes Designs | 2018/11/9 | ||||
| 應用說明 | DS15BA101 & DS15EA101 Enable Long Reach Applications for Embedded Clock SER/DES (Rev. E) | 2013/4/29 | ||||
| 使用指南 | LX21EVK01 Channel Link III Ser/Des Evaluation Kit | 2012/2/1 |
設計與開發
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LX21EVK01 — LX21EVK01 評估套件
The LX21EVK01 is an evaluation kit designed to demonstrate the performance and capabilities of the DS92LX2121 and DS92LX2122 Channel Link III Serializer/Deserializer chipset.
The DS92LX2121 serializer board accepts LVCMOS input signals for the high speed forward channel and provides additional (...)
| 封裝 | 針腳 | CAD 符號、佔位空間與 3D 模型 |
|---|---|---|
| WQFN (RTA) | 40 | Ultra Librarian |