開發模組 (EVM) 的 GUI
LMH6401
- 3-dB Bandwidth: 4.5 GHz at 26-dB Gain
- Gain Range: –6 dB to 26 dB in 1-dB Steps
- Differential Input Impedance: 100 Ω
- Differential Output with Common-Mode Control
- Distortion at Max Gain (VO = 2 VPPD, RL = 200 Ω):
- 200 MHz: HD2 at –73 dBc, HD3 at –80 dBc
- 500 MHz: HD2 at –68 dBc, HD3 at –72 dBc
- 1 GHz: HD2 at –63 dBc, HD3 at –63 dBc
- 2 GHz: HD2 at –58 dBc, HD3 at –54 dBc
- Output IP3:
- 43 dBm at 200 MHz
- 33 dBm at 1 GHz
- 27 dBm at 2 GHz
- Output IP2:
- 67 dBm at 200 MHz
- 60 dBm at 1 GHz
- 52 dBm at 2 GHz
- 8-dB Noise Figure at 1 GHz, RS = 100 Ω
- 82-ps Rise, Fall Time Pulse Response
- Supply Operation: 5.0 V at 69 mA
- Supports Single- and (±) Split-Supply Operation:
- DC- and AC-Coupled Applications
- Fabricated on an Advanced Complementary BiCMOS Process
- 3-mm × 3-mm UQFN-16 Package
The LMH6401 is a wideband, digitally-controlled, variable-gain amplifier (DVGA) designed for dc to radio frequency (RF), intermediate frequency (IF), and high-speed time-domain applications. The device is an ideal analog-to-digital converter (ADC) driver for dc- or ac-coupled applications that require an automatic gain control (AGC).
Noise and distortion performance is optimized to drive ultra-wideband ADCs. The amplifier has an 8-dB noise figure at maximum gain and a –63-dBc harmonic distortion at 1 GHz for full-scale signal levels. The device supports both single- and split-supply operation for driving an ADC. A common-mode reference input pin is provided to align the amplifier output common-mode with the ADC input requirements.
Gain control is performed via an SPI™ interface, allowing a 32-dB gain range from –6 dB to 26 dB in 1-dB steps. A power-down feature is also available through the external PD pin or SPI control.
This level of performance is achieved at a low power level of 345 mW. The operating ambient temperature range is –40°C to 85°C.
技術文件
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檢視所有 8 | 類型 | 標題 | 日期 | ||
|---|---|---|---|---|
| * | Data sheet | LMH6401 DC to 4.5 GHz, Fully-Differential, Digital Variable-Gain Amplifier datasheet (Rev. A) | PDF | HTML | 2015年 5月 19日 |
| E-book | The Signal e-book: A compendium of blog posts on op amp design topics | 2017年 3月 28日 | ||
| Application note | ADC32RF45: Amplifier to ADC Interface (Rev. A) | 2016年 9月 7日 | ||
| Technical article | Disentangle RF amplifier specs: output voltage/current and 1dB compression point | PDF | HTML | 2016年 6月 9日 | |
| Technical article | Disentangle RF amplifier specs: intermodulation distortion and intercept points | PDF | HTML | 2016年 4月 19日 | |
| Technical article | Disentangling RF amplifier specs: amplifier spot noise vs. noise figure | PDF | HTML | 2016年 2月 5日 | |
| EVM User's guide | TSW54J60 Evaluation Module User's Guide (Rev. A) | 2015年 9月 21日 | ||
| EVM User's guide | LMH6401 EVM User's Guide (Rev. A) | 2015年 5月 29日 |
設計與開發
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開發板
LMH6401EVM — LMH6401 評估模組
The LMH6401 Evaluation module (EVM) is used to evaluate the single LMH6401, digitally-controlled variable-gain amplifier (DVGA) in a 16-lead high-performance RF package. The EVM is designed to quickly and easily demonstrate the functionality and performance of LMH6401 across all the gain (...)
使用指南: PDF
參考設計
TIDA-01022 — 適用於 DSO、雷達和 5G 無線測試系統的靈活 3.2-GSPS 多通道 AFE 參考設計
This high speed multi-channel data capture reference design enables optimum system performance. System designers needs to consider critical design parameters like clock jitter and skew for high speed multi-channel clock generation, which affects overall system SNR, SFDR, channel to channel skew (...)
參考設計
TIDA-01028 — 適用於高速示波器和寬頻帶數位器的 12.8-GSPS 類比前端參考設計
This reference design provides a practical example of interleaved RF-sampling analog-to-digital converters (ADCs) to achieve a 12.8-GSPS sampling rate. This is done by time interleaving two RF-sampling ADCs. Interleaving requires a phase shift between the ADCs, which this reference design achieves (...)
參考設計
TIDA-010128 — 適用於 12 位元數位器的可擴充 20.8 GSPS 參考設計
This reference design describes a 20.8 GSPS sampling system using RF sampling analog-to-digital converters (ADCs) in time interleaved configuration. Time interleaving method is a proven and traditional way of increasing sample rate, however, matching individual ADCs offset, gain and sampling time (...)
參考設計
TIDA-010122 — 適用於多通道射頻系統的參考設計同步數據轉換器 DDC 和 NCO 功能
此參考設計可解決與新興 5G 適配應用相關，例如大規模多輸入多輸出 (mMIMO)、相位陣列雷達與通訊酬載等應用相關的同步設計挑戰。一般 RF 前端包含天線、低雜訊放大器 (LNA)、混波器、類比網域中的本地振盪器 (LO) 及類比轉數位轉換器、數值控制振盪器 (NCO) 和數位降轉換器 (DDC)。為了達到整體系統同步化，這些數位區塊必須與系統時鐘同步。本參考設計採用 ADC12DJ3200 資料轉換器，透過同步處理晶片內建 NCO 與 SYNC ~ 並使用無雜訊孔徑延遲調整 (tAD 調整) 功能，在多個接收器之間達到小於 5-ps 的頻道間偏斜的效果，以進一步降低偏斜。此設計也具備搭載 (...)
參考設計
TIDA-00823 — 具有 AC 與 DC 耦合固定增益放大器的 16 位元 1 GSPS 數位器參考設計
This reference design discusses the use and performance of the Ultra-Wideband, Fixed-gain high-speed amplifier, the LMH3401 to drive the high-speed analog-to-digital converter (ADC), the ADS54J60 device. Different options for common-mode voltages, power supplies, and interfaces are discussed and (...)
參考設計
TIDA-00826 — 50 Ohm 2 GHz 示波器前端參考設計
This reference design is part of an analog front-end for 50Ω-input oscilloscope application. System designers can readily use this evaluation platform to process input signals from DC to 2 GHz in both frequency-domain and time-domain applications.
參考設計
TIDA-00822 — 具有 AC 與 DC 耦合可變增益放大器的 16 位元 1 GSPS 數位器參考設計
This reference design discusses the use and performance of the Digital Variable-Gain high-speed amplifier, the LMH6401, to drive the high-speed analog-to-digital converter (ADC), the ADS54J60 device. Different options for common-mode voltages, power supplies, and interfaces are discussed and (...)
參考設計
TIDA-00654 — 串接 LMH5401 和 LMH6401 參考設計
A wideband single-ended to differential conversion reference design in both DC- and AC- coupled applications is presented. The design evaluates the performance of the LMH5401 and LMH6401 cascade and offers insight into the design.
| 封裝 | 引腳 | 下載 |
|---|---|---|
| UQFN-HR (RMZ) | 16 | 檢視選項 |
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