Scalable 20.8 GSPS reference design for 12 bit digitizers


Design files


This reference design describes a 20.8 GSPS sampling system using RF sampling analog-to-digital converters (ADCs) in time interleaved configuration. Time interleaving method is a proven and traditional way of increasing sample rate, however, matching individual ADCs offset, gain and sampling time mismatch is critical to achieve performance. The complexity of interleaving increases with higher sampling clock. The phase matching between the ADCs is one of the critical specifications to achieve better SFDR and ENOB. This reference design uses the noiseless aperture delay adjustment feature on ADC12DJ5200RF with a 19 fs precise phase control steps that eases 20.8 GSPS interleaving implementation. The reference design uses on-board low noise JESD204B clock generator based on LMK04828 and LMX2594 that meets 12 bit system performance requirement.

  • 20.8 GSPS Time interleaved 12-bit RF-sampling ADCs
  • 6 GHz Analog front end
  • Fine sample clock phase adjustment (19 fs resolution)
  • Phase synchronization of multiple ADCs
  • Companion power reference design with a >85% efficiency at 12-V input
  • JESD204B supporting 8, 16, or 32 JESD lanes, data rates up to 12.8 Gbps per lane
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A fully assembled board has been developed for testing and performance validation only, and is not available for sale.

Design files & products

Design files

Download ready-to-use system files to speed your design process.

TIDUER5.PDF (11798 K)

Reference design overview and verified performance test data

TIDUEI2.PDF (6295 K)

Reference design overview and verified performance test data

TIDRZR1.PDF (3344 K)

Detailed schematic diagram for design layout and components

TIDRZ71A.PDF (240 K)

Complete listing of design components, reference designators, and manufacturers/part numbers

TIDRZR2.PDF (2981 K)

Detailed overview of design layout for component placement

TIDRZR4.ZIP (37212 K)

Files used for 3D models or 2D drawings of IC components

TIDCFH0.ZIP (13521 K)

Design file that contains information on physical board layer of design PCB

TIDRZR3.PDF (28701 K)

PCB layer plot file used for generating PCB design layout


Includes TI products in the design and potential alternatives.

High-speed ADCs (≥10 MSPS)

ADC12DJ5200RFRF-sampling 12-bit ADC with dual-channel 5.2 GSPS or single-channel 10.4 GSPS

Data sheet: PDF | HTML
AND gates

SN74LVC1G081-ch, 2-input 1.65-V to 5.5-V 32 mA drive strength AND gate

Data sheet: PDF
Analog switches & muxes

SN74LVC2G535-V, 2:1 (SPDT), 1-channel general-purpose analog switch (available in the NanoFree™ package)

Data sheet: PDF | HTML
Clock buffers

LMK003043.1-GHz differential clock buffer/level translator with 4 configurable outputs

Data sheet: PDF | HTML
Clock jitter cleaners & synchronizers

LMK04828Ultra low-noise JESD204B compliant clock jitter cleaner with integrated 2370 to 2630-MHz VCO0.

Data sheet: PDF | HTML

LMC6762Dual Micro-Power Rail-to-Rail Input CMOS Comparator with Push-Pull Output

Data sheet: PDF
Digital temperature sensors

LM95233±2°C Dual Remote and Local Temperature Sensor with TruTherm Technology and SMBus Interface

Data sheet: PDF
Direction-controlled voltage translators

SN74AVC4T774Four-bit dual-supply bus transceiver with configurable voltage-level shifting and tri-state outputs

Data sheet: PDF | HTML
I2C general-purpose I/Os (GPIOs)

TCA9534A8-bit 1.65- to 5.5-V I2C/SMBus I/O expander with interrupt, & config registers

Data sheet: PDF | HTML

DS90LT012AQ-Q1Automotive LVDS differential line receiver

Data sheet: PDF

DS90LV028AQ-Q1Automotive LVDS dual differential line receiver

Data sheet: PDF | HTML
Linear & low-dropout (LDO) regulators

TLV702300-mA, high-PSRR, low-IQ, low-dropout voltage regulator with enable

Data sheet: PDF | HTML
Linear & low-dropout (LDO) regulators

TPS7A331-A, high-PSRR, negative, adjustable low-dropout voltage regulator with enable

Data sheet: PDF | HTML
Linear & low-dropout (LDO) regulators

TPS7A83002-A, low-VIN, low-2-A, low-VIN, low-noise, ultra-low-dropout voltage regulator with power good wi

Data sheet: PDF | HTML
Linear & low-dropout (LDO) regulators

TPS7A843-A, low-VIN, low-noise, ultra-low-dropout voltage regulator with power good with high-accuracy

Data sheet: PDF | HTML

CSD15571Q220-V, N channel NexFET™ power MOSFET, single SON 2 mm x 2 mm, 19.2 mOhm

Data sheet: PDF
Noninverting buffers & drivers

SN74LVC1G125Single 1.65-V to 5.5-V buffer with 3-state outputs

Data sheet: PDF | HTML

LMK61E2156.250-MHz, ±50 ppm, ultra-low jitter, integrated EEPROM, fully programmable oscillator

Data sheet: PDF | HTML
Power modules (integrated inductor)

TPS8213017-V input 3-A step-down converter module with integrated inductor

Data sheet: PDF | HTML

LMH54018-GHz Ultra wideband fully differential amplifier

Data sheet: PDF | HTML
RF PLLs & synthesizers

LMX259415-GHz wideband PLLatinum™ RF synthesizer with phase synchronization and JESD204B support

Data sheet: PDF | HTML

LMH64014.5 GHz ultra wideband digital variable gain amplifier

Data sheet: PDF | HTML
eFuses & hot swap controllers

TPS259264.5-V to 13.8-V, 30mΩ, 2-5A eFuse

Data sheet: PDF | HTML

Technical documentation

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Type Title Date
* Design guide Scalable 20.8 GSPS Reference Design for 12-bit Digitizers May 22, 2019
Technical article Step-by-step considerations for designing wide-bandwidth multichannel systems PDF | HTML Jun. 04, 2019
Design guide 12.8-GSPS analog front end reference design for high-speed oscilloscope and wide Mar. 05, 2019
White paper Interleaving ADCs for Higher Sample Rates Feb. 01, 2005
Application note Defining Skew, Propagation-Delay, Phase Offset (Phase Error) Nov. 28, 2001

Related design resources

Hardware development

ADC12DJ5200RFEVM ADC12DJ5200RF RF-sampling 12-bit dual 5.2-GSPS or single 10.4-GSPS ADC evaluation module TSW14J57EVM Data capture/pattern generator: data converter EVM with 16 JESD204B lanes from 1.6-15Gbps

Reference designs

TIDA-01027 Low-noise power supply reference design maximizing performance in 12.8-GSPS data acquisition systems

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