Reference design synchronizing data converter DDC and NCO features for multi-channel RF systems


Design files


This reference design addresses synchronization design challenges associated with emerging 5G adapted applications like massive multiple input multiple output (mMIMO), phase array radar and communication payload. The typical RF front end contains antenna, low-noise amplifier (LNA), mixer, local oscillator (LO) in analog domain and analog-to-digital converter, numerical-controlled oscillator (NCO) and digital down converter (DDC) in digital domain. To achieve overall system synchronization, these digital blocks need to be synchronized with a system clock. This reference design uses ADC12DJ3200 data converter to achieve less than 5-ps channel-to-channel skew across multiple receiver with deterministic latency by synchronizing on-chip NCO with SYNC~ and uses noiseless aperture delay adjustment (tAD Adjust) feature to further reduce skew. This design also provides a very low-phase noise clocking based on LMX2594 wideband PLL and LMK04828 synthesizer and jitter cleaner.

  • Four-channel, 3.2-GSPS, 6-GHz high-speed analog front end
  • On-chip NCO synchronization allows synchronization across multiple ADCs using SYNC~
  • Multi-channel JESD204B-compliant clock
  • JESD204B supporting eight, 16 or 32 JESD lanes and data rates up to 12.8 Gbps per lane
  • Companion power reference design with a >85% efficiency at 12-V input
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A fully assembled board has been developed for testing and performance validation only, and is not available for sale.

Design files & products

Design files

Download ready-to-use system files to speed your design process.

TIDUEQ6.PDF (11539 K)

Reference design overview and verified performance test data

TIDRZV5.PDF (3461 K)

Detailed schematic diagram for design layout and components


Complete listing of design components, reference designators, and manufacturers/part numbers

TIDRZV7.PDF (2983 K)

Detailed overview of design layout for component placement

TIDRZV9.ZIP (74323 K)

Files used for 3D models or 2D drawings of IC components

TIDCFI4.ZIP (13521 K)

Design file that contains information on physical board layer of design PCB

TIDRZV8.PDF (28658 K)

PCB layer plot file used for generating PCB design layout


Includes TI products in the design and potential alternatives.

High-speed ADCs (≥10 MSPS)

ADC12DJ320012-bit, dual 3.2-GSPS or single 6.4-GSPS, RF-sampling analog-to-digital converter (ADC)

Data sheet: PDF | HTML
AND gates

SN74LVC1G081-ch, 2-input 1.65-V to 5.5-V 32 mA drive strength AND gate

Data sheet: PDF
Analog switches & muxes

SN74LVC2G535-V, 2:1 (SPDT), 1-channel general-purpose analog switch (available in the NanoFree™ package)

Data sheet: PDF | HTML
Clock buffers

LMK003043.1-GHz differential clock buffer/level translator with 4 configurable outputs

Data sheet: PDF | HTML
Clock jitter cleaners & synchronizers

LMK04828Ultra low-noise JESD204B compliant clock jitter cleaner with integrated 2370 to 2630-MHz VCO0.

Data sheet: PDF | HTML

LMC6762Dual Micro-Power Rail-to-Rail Input CMOS Comparator with Push-Pull Output

Data sheet: PDF
Digital temperature sensors

LM95233±2°C Dual Remote and Local Temperature Sensor with TruTherm Technology and SMBus Interface

Data sheet: PDF
Direction-controlled voltage translators

SN74AVC4T774Four-bit dual-supply bus transceiver with configurable voltage-level shifting and tri-state outputs

Data sheet: PDF | HTML
I2C general-purpose I/Os (GPIOs)

TCA9534A8-bit 1.65- to 5.5-V I2C/SMBus I/O expander with interrupt, & config registers

Data sheet: PDF | HTML

DS90LT012AQ-Q1Automotive LVDS differential line receiver

Data sheet: PDF

DS90LV028AQ-Q1Automotive LVDS dual differential line receiver

Data sheet: PDF | HTML
Linear & low-dropout (LDO) regulators

TLV702300-mA, high-PSRR, low-IQ, low-dropout voltage regulator with enable

Data sheet: PDF | HTML
Linear & low-dropout (LDO) regulators

TPS7A331-A, high-PSRR, negative, adjustable low-dropout voltage regulator with enable

Data sheet: PDF | HTML
Linear & low-dropout (LDO) regulators

TPS7A83002-A, low-VIN, low-2-A, low-VIN, low-noise, ultra-low-dropout voltage regulator with power good wi

Data sheet: PDF | HTML
Linear & low-dropout (LDO) regulators

TPS7A843-A, low-VIN, low-noise, ultra-low-dropout voltage regulator with power good with high-accuracy

Data sheet: PDF | HTML

CSD15571Q220-V, N channel NexFET™ power MOSFET, single SON 2 mm x 2 mm, 19.2 mOhm

Data sheet: PDF
Noninverting buffers & drivers

SN74LVC1G125Single 1.65-V to 5.5-V buffer with 3-state outputs

Data sheet: PDF | HTML

LMK61E2156.250-MHz, ±50 ppm, ultra-low jitter, integrated EEPROM, fully programmable oscillator

Data sheet: PDF | HTML
Power modules (integrated inductor)

TPS8213017-V input 3-A step-down converter module with integrated inductor

Data sheet: PDF | HTML

LMH54018-GHz Ultra wideband fully differential amplifier

Data sheet: PDF | HTML
RF PLLs & synthesizers

LMX259415-GHz wideband PLLatinum™ RF synthesizer with phase synchronization and JESD204B support

Data sheet: PDF | HTML

LMH64014.5 GHz ultra wideband digital variable gain amplifier

Data sheet: PDF | HTML
eFuses & hot swap controllers

TPS259264.5-V to 13.8-V, 30mΩ, 2-5A eFuse

Data sheet: PDF | HTML

Technical documentation

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Type Title Date
* Design guide Reference Design Synchronizing Data Converter DDC and NCO Features for Multi-cha Jun. 13, 2019
Application note JESD204B Multi-Device Synchronization Using LMK0461x Aug. 16, 2017
Analog Design Journal JESD204B multi-device synchronization: Breaking down the requirements Apr. 28, 2015
Application note Defining Skew, Propagation-Delay, Phase Offset (Phase Error) Nov. 28, 2001

Related design resources

Hardware development

ADC12DJ3200EVM ADC12DJ3200 12-bit, dual 3.2-GSPS or single 6.4-GSPS, RF-sampling ADC evaluation module TSW14J57EVM Data capture/pattern generator: data converter EVM with 16 JESD204B lanes from 1.6-15Gbps

Reference designs

TIDA-01027 Low-noise power supply reference design maximizing performance in 12.8-GSPS data acquisition systems

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