This reference design provides a practical example of interleaved RF-sampling analog-to-digital converters (ADCs) to achieve a 12.8-GSPS sampling rate. This is done by time interleaving two RF-sampling ADCs. Interleaving requires a phase shift between the ADCs, which this reference design achieves using the Noiseless Aperture Delay Adjustment (tAD Adjust) feature of the ADC12DJ3200. This feature is also used to minimize mismatches typical of interleaved ADCs: maximizing SNR, ENOB and SFDR performance. A low-phase noise clocking tree with JESD204B support is also featured on this reference design. It is implemented using the LMX2594 wideband PLL and the LMK04828 synthesizer and jitter cleaner.
A fully assembled board has been developed for testing and performance validation only, and is not available for sale.
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Reference design overview and verified performance test data
Detailed schematic diagram for design layout and components
Complete listing of design components, reference designators, and manufacturers/part numbers
Detailed overview of design layout for component placement
Files used for 3D models or 2D drawings of IC components
Design file that contains information on physical board layer of design PCB
PCB layer plot file used for generating PCB design layout
Includes TI products in the design and potential alternatives.
| Type | Title | Date | ||
|---|---|---|---|---|
| * | Design guide | 12.8-GSPS analog front end reference design for high-speed oscilloscope and wide | Mar. 05, 2019 | |
| Technical article | Step-by-step considerations for designing wide-bandwidth multichannel systems | Jun. 04, 2019 | ||
| White paper | Interleaving ADCs for Higher Sample Rates | Feb. 01, 2005 | ||
| Application note | Defining Skew, Propagation-Delay, Phase Offset (Phase Error) | Nov. 28, 2001 |
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