LMK1C1106
- High-performance 1:6 and 1:8 LVCMOS clock buffer
- Very low output skew < 55 ps
- Extremely low additive jitter < 25-fs nominal
- 12-fs typical at VDD = 3.3 V
- 15-fs typical at VDD = 2.5 V
- 28-fs typical at VDD = 1.8 V
- Very low propagation delay < 3 ns
- Synchronous output enable
- Supply voltage: 3.3 V, 2.5 V, or 1.8 V
- 3.3-V tolerant input at all supply voltages
- Fail-safe inputs
- Industry high ESD rating of 9000 V HBM
- fmax = 250 MHz for 3.3 V fmax = 200-MHz for 2.5 V and 1.8 V
- Operating temperature range: –40°C to 125°C
- Available in 14-pin and 16-pin TSSOP package
The LMK1C110x is a modular, high-performance, low-skew, general-purpose clock buffer family from Texas Instruments. The entire family is designed with a modular approach in mind. Five different fan-out variations, 1:2, 1:3, 1:4, 1:6 and 1:8 are available.
All of the devices within this family are pin-compatible to each other and backwards compatible to the CDCLVC110x family for easy handling.
All family members share the same high performing characteristics such as low additive jitter, low skew, and wide operating temperature range.
The LMK1C110x supports a synchronous output enable control (1G) which switches the outputs into a low state when 1G is low. These devices have a fail-safe input that prevents oscillation at the outputs in the absence of an input signal and allows for input signals before VDD is supplied.
The LMK1C110x family operates in a 1.8-V, 2.5-V and 3.3-V environment and are characterized for operation from –40°C to 125°C.
技術文件
| 重要文件 | 類型 | 標題 | 格式選項 | 下載最新的英文版本 | 日期 | |
|---|---|---|---|---|---|---|
| * | 資料表 | LMK1C110x 1.8-V, 2.5-V, and 3.3-V LVCMOS Clock Buffer Family datasheet (Rev. A) | PDF | HTML | 2022/1/20 | ||
| 應用說明 | Sine to Square Wave Conversion Using Clock Buffers | PDF | HTML | 2024/9/3 |
設計與開發
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| 封裝 | 針腳 | CAD 符號、佔位空間與 3D 模型 |
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訂購與品質
建議產品可能具有與此 TI 產品相關的參數、評估模組或參考設計。