LMK61E0M

現行

具有內部 EEPROM 的 LVCMOS 超低抖動可編程振盪器

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產品規格表

document-pdfAcrobat LMK61E0M Ultra-Low Jitter Programmable Oscillator With Internal EEPROM datasheet (Rev. A) (英文) PDF | HTML

LMK61E0M

現行

產品規格表

立即訂購

產品詳細資料

Output type

LVCMOS

Output frequency (MHz)

200

Stability (ppm)

25

Operating temperature range (°C)

-40 to 85

Jitter (ps)

0.5

Output type

LVCMOS

Output frequency (MHz)

200

Stability (ppm)

25

Operating temperature range (°C)

-40 to 85

Jitter (ps)

0.5

QFM (SIA)

8

12.25 mm² (3.5 mm × 3.5 mm)

Ultra-Low Noise, High Performance
- Jitter: 500-fs RMS Typical f_OUT > 50 MHz on LMK61E0M
LMK61E0M Supports 3.3-V LVCMOS Output up to 200 MHz
Total Frequency Tolerance of ±25 ppm
System Level Features
- Glitch-Less Frequency Margining: Up to ±1000 ppm From Nominal
- Internal EEPROM: User Configurable Start-Up Settings
Other Features
- Device Control: Fast Mode I²C up to 1000 kHz
- 3.3-V Operating Voltage
- Industrial Temperature Range (–40ºC to +85ºC)
- 7-mm × 5-mm 8-Pin Package
Default Frequency: 70.656 MHz

Ultra-Low Noise, High Performance
- Jitter: 500-fs RMS Typical f_OUT > 50 MHz on LMK61E0M
LMK61E0M Supports 3.3-V LVCMOS Output up to 200 MHz
Total Frequency Tolerance of ±25 ppm
System Level Features
- Glitch-Less Frequency Margining: Up to ±1000 ppm From Nominal
- Internal EEPROM: User Configurable Start-Up Settings
Other Features
- Device Control: Fast Mode I²C up to 1000 kHz
- 3.3-V Operating Voltage
- Industrial Temperature Range (–40ºC to +85ºC)
- 7-mm × 5-mm 8-Pin Package
Default Frequency: 70.656 MHz

The LMK61E0 family of ultra-low jitter PLLatinum^TM programmable oscillators use fractional-N frequency synthesizers with integrated VCOs to generate commonly used reference clocks. The LMK61E0M supports 3.3-V LVCMOS outputs. The device features self start-up from on-chip EEPROM to generate a factory programmed default output frequency, or the device registers and EEPROM settings are fully programmable in-system through I²C serial interface. The device provides fine and coarse frequency margining control through I²C serial interface, making it a digitally-controlled oscillator (DCXO).

The PLL feedback divider can be updated to adjust the output frequency without spikes or glitches in steps of <1ppb using a PFD of 12.5 MHz (R divider=4, doubler disabled) for compatibility with xDSL requirements, or in steps of <5.2 ppb using a PFD of 100 MHz (R divider=1, doubler enabled) for compatibility with broadcast video requirements. The frequency margining features also facilitate system design verification tests (DVT), such as standards compliance and system timing margin testing.

The LMK61E0 family of ultra-low jitter PLLatinum^TM programmable oscillators use fractional-N frequency synthesizers with integrated VCOs to generate commonly used reference clocks. The LMK61E0M supports 3.3-V LVCMOS outputs. The device features self start-up from on-chip EEPROM to generate a factory programmed default output frequency, or the device registers and EEPROM settings are fully programmable in-system through I²C serial interface. The device provides fine and coarse frequency margining control through I²C serial interface, making it a digitally-controlled oscillator (DCXO).

The PLL feedback divider can be updated to adjust the output frequency without spikes or glitches in steps of <1ppb using a PFD of 12.5 MHz (R divider=4, doubler disabled) for compatibility with xDSL requirements, or in steps of <5.2 ppb using a PFD of 100 MHz (R divider=1, doubler enabled) for compatibility with broadcast video requirements. The frequency margining features also facilitate system design verification tests (DVT), such as standards compliance and system timing margin testing.

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重要文件	類型	標題	格式選項	下載最新的英文版本		日期
*	資料表	LMK61E0M Ultra-Low Jitter Programmable Oscillator With Internal EEPROM datasheet (Rev. A)	PDF \| HTML			2017/5/16

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LMK61E0MEVM — LMK61E0M 超低抖動可程式編輯振盪器評估模組

LMK61E0MEVM 評估模組提供完整平台，透過整合式 EEPROM 和擴充頻率裕度功能，評估德州儀器 LMK61E0M 超低抖動可編程振盪器的抖動性能和可配置性。

LMK61E0MEVM 可用作抖動關鍵應用的高性能時脈來源使用，並可輕鬆自訂為使用者所需的任何頻率。板載 USB 轉 I2C 介面允許透過軟體圖形使用者介面 (GUI) 配置裝置，且不需要外部輸入或電源即可進行裝置運作。邊緣啟動 SMA 連接埠可存取 LMK61E0M 的雙 LVCMOS 時脈輸出，以使用市售同軸纜線、轉接器或平衡不平衡轉換器（未隨附）介接測試設備或參考電路板。

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PLLATINUMSIM-SW — PLL 迴路濾波器、相位雜訊、鎖定時間與雜散模擬工具

PLLATINUMSIM-SW 為一模擬工具，可讓使用者建立 PLLatinum™ 積體電路的詳細設計和模擬，包括 LMX 系列的相位鎖定迴路 (PLL) 及合成器。

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LMK61E0M

具有內部 EEPROM 的 LVCMOS 超低抖動可編程振盪器

LMK61E0M

產品詳細資料

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功能相同，但針腳輸出與所比較的裝置不同。

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設計與開發

LMK61E0MEVM — LMK61E0M 超低抖動可程式編輯振盪器評估模組

TICSPRO-SW — TICS Pro GUI and Live Programming Tool for Clocking Devices

CLOCK-TREE-ARCHITECT — 時鐘樹架構程式設計軟體

PLLATINUMSIM-SW — PLL 迴路濾波器、相位雜訊、鎖定時間與雜散模擬工具

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