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PCM5102-Q1

不推薦在新設計中採用

具 2VRMS 輸出和整合式音訊 PLL 的汽車類 112dB 立體聲道 DAC

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PCM5102-Q1 不建議用於新設計
此產品將繼續向現有客戶提供。新設計應考量替代產品。
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PCM5102A-Q1 現行 具有 32 位元、384kHz PCM 介面的汽車類 2VRMS DirectPath™、112dB 音訊立體聲道 DAC This product is CMOS-integrated circuit that includes a stereo digital-to-analog converter and additional support circuitry in a small TSSOP package.

PCM5102-Q1

不推薦在新設計中採用
產品規格表 立即訂購

產品詳細資料

Number of DAC channels 2 Analog inputs 0 Analog outputs 2 DAC SNR (typ) (dB) 112 Sampling rate (max) (kHz) 384 Control interface HW Resolution (Bits) 32 Architecture Delta Sigma with line driver Operating temperature range (°C) -40 to 105 Rating Automotive
Number of DAC channels 2 Analog inputs 0 Analog outputs 2 DAC SNR (typ) (dB) 112 Sampling rate (max) (kHz) 384 Control interface HW Resolution (Bits) 32 Architecture Delta Sigma with line driver Operating temperature range (°C) -40 to 105 Rating Automotive
TSSOP (PW) 20 41.6 mm² 6.5 x 6.4
  • Qualified for Automotive Applications
  • AEC-Q100 Qualified With the Following Results:
    • Device Temperature Grade 2: –40°C to 105°C Ambient
      Operating Temperature Range
    • Device HBM ESD Classification Level H2
    • Device CDM ESD Classification Level C3B
  • Market-Leading Low Out-of-Band Noise
  • Selectable Digital-Filter Latency and Performance
  • No DC Blocking Capacitors Required
  • Integrated Negative Charge Pump
  • Internal Pop-Free Control For Sample-Rate Changes or Clock Halts
  • Intelligent Muting System; Soft Up/Down Ramp
    and Analog Mute For 120-dB Mute SNR With Popless Operation.
  • Integrated High-Performance Audio PLL With BCK Reference to
    Generate SCK Internally
  • Small 20-pin TSSOP Package

Other Key Features

  • Accepts 16-, 24-, and 32-Bit Audio Data
  • PCM Data Formats: I2S, Left-Justified
  • Automatic Power-Save Mode When LRCK And BCK Are Deactivated
  • 3.3-V Failsafe LVCMOS Digital Inputs
  • Hardware Configuration
  • Single-Supply Operation:
    • 3.3-V Analog, 3.3-V Digital
  • Integrated Power-On Reset
  • Qualified for Automotive Applications
  • AEC-Q100 Qualified With the Following Results:
    • Device Temperature Grade 2: –40°C to 105°C Ambient
      Operating Temperature Range
    • Device HBM ESD Classification Level H2
    • Device CDM ESD Classification Level C3B
  • Market-Leading Low Out-of-Band Noise
  • Selectable Digital-Filter Latency and Performance
  • No DC Blocking Capacitors Required
  • Integrated Negative Charge Pump
  • Internal Pop-Free Control For Sample-Rate Changes or Clock Halts
  • Intelligent Muting System; Soft Up/Down Ramp
    and Analog Mute For 120-dB Mute SNR With Popless Operation.
  • Integrated High-Performance Audio PLL With BCK Reference to
    Generate SCK Internally
  • Small 20-pin TSSOP Package

Other Key Features

  • Accepts 16-, 24-, and 32-Bit Audio Data
  • PCM Data Formats: I2S, Left-Justified
  • Automatic Power-Save Mode When LRCK And BCK Are Deactivated
  • 3.3-V Failsafe LVCMOS Digital Inputs
  • Hardware Configuration
  • Single-Supply Operation:
    • 3.3-V Analog, 3.3-V Digital
  • Integrated Power-On Reset

The PCM510x-Q1 family is a series of monolithic CMOS integrated circuits that include a stereo digital-to-analog converter and additional support circuitry in a small TSSOP package. The PCM510x-Q1 uses the latest generation of TI’s advanced segment-DAC architecture to achieve excellent dynamic performance and improved tolerance to clock jitter.

The PCM510x-Q1 provides 2.1-VRMS ground-centered outputs, allowing designers to eliminate not only dc blocking capacitors on the output, but also external muting circuits traditionally associated with single-supply line drivers.

The integrated line driver surpasses all other charge-pump-based line drivers by supporting loads down to 1 kΩ. By supporting loads down to 1 k&3937;, the PCM510x-Q1 can essentially drive up to 10 products in parallel (LCD TV, DVDR, AV receivers, and so on).

The integrated PLL on the device removes the requirement for a system clock (commonly known as master clock). This allows a three-wire I2S connection, along with reduced system EMI.

Intelligent clock error and PowerSense undervoltage protection uses a two-level mute system for pop-free performance. On clock error or system power failure, the device digitally attenuates the data (or last known-good data), then mutes the analog circuit

Compared with existing DAC technology, the PCM510x-Q1 offers up to 20-dB lower out-of-band (OBN) noise, reducing EMI and aliasing in downstream amplifiers/ADCs. (from traditional 100-kHz OBN measurements all the way to 3 MHz)

The PCM510x-Q1 accepts industry-standard audio data formats with 16- to 32-bit data and supports sSample rates up to 384 kHz.

The PCM510x-Q1 family is a series of monolithic CMOS integrated circuits that include a stereo digital-to-analog converter and additional support circuitry in a small TSSOP package. The PCM510x-Q1 uses the latest generation of TI’s advanced segment-DAC architecture to achieve excellent dynamic performance and improved tolerance to clock jitter.

The PCM510x-Q1 provides 2.1-VRMS ground-centered outputs, allowing designers to eliminate not only dc blocking capacitors on the output, but also external muting circuits traditionally associated with single-supply line drivers.

The integrated line driver surpasses all other charge-pump-based line drivers by supporting loads down to 1 kΩ. By supporting loads down to 1 k&3937;, the PCM510x-Q1 can essentially drive up to 10 products in parallel (LCD TV, DVDR, AV receivers, and so on).

The integrated PLL on the device removes the requirement for a system clock (commonly known as master clock). This allows a three-wire I2S connection, along with reduced system EMI.

Intelligent clock error and PowerSense undervoltage protection uses a two-level mute system for pop-free performance. On clock error or system power failure, the device digitally attenuates the data (or last known-good data), then mutes the analog circuit

Compared with existing DAC technology, the PCM510x-Q1 offers up to 20-dB lower out-of-band (OBN) noise, reducing EMI and aliasing in downstream amplifiers/ADCs. (from traditional 100-kHz OBN measurements all the way to 3 MHz)

The PCM510x-Q1 accepts industry-standard audio data formats with 16- to 32-bit data and supports sSample rates up to 384 kHz.
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類型 標題 日期
* Data sheet 2Vrms DirectPath,112/106/100dB Audio Stereo DAC with 32-bit, 384kHz PCM IF datasheet (Rev. C) 2013年 4月 12日

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  • 產品標記
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  • MSL 等級/回焊峰值
  • MTBF/FIT 估算值
  • 材料內容
  • 認證摘要
  • 進行中持續性的可靠性監測
內含資訊：
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