SCAN921260
- IEEE 1149.1 (JTAG) Compliant and At-Speed BIST Test Modes
- Deserializes One to Six BusLVDS Input Serial Data Streams With Embedded Clocks
- Seven Selectable Serial Inputs to Support N+1 Redundancy of Deserialized Streams
- Seventh Channel Has Single Pin Monitor Output That Reflects Input From Seventh Channel Input
- Parallel Clock Rate Up To 66 MHz
- On Chip Filtering for PLL
- High Impedance Inputs Upon Power Off (Vcc = 0V)
- Single Power Supply at +3.3V
- 196-Pin NFBGA Package (Low-Profile Ball Grid Array) Package
- Industrial Temperature Range Operation: −40 to +85
All trademarks are the property of their respective owners.
The SCAN921260 integrates six deserializer devices into a single chip. The SCAN921260 can simultaneously deserialize up to six data streams that have been serialized by the Texas Instruments SCAN921023 Bus LVDS serializer. The device also includes a seventh serial input channel that serves as a redundant input.
Each deserializer block in the SCAN921260 operates independently with its own clock recovery circuitry and lock-detect signaling.
The SCAN921260 uses a single +3.3V power supply with an estimated power dissipation of 1.2W at 3.3V with a PRBS-15 pattern. Refer to the Connection Diagrams for packaging information.
您可能會感興趣的類似產品
功能相同，但針腳輸出與所比較的裝置不同。
技術文件
找不到結果。請清除您的搜尋條件，然後再試一次。
檢視所有 2
| 重要文件 | 類型 | 標題 | 格式選項 | 下載最新的英文版本 | 日期 | |
|---|---|---|---|---|---|---|
| * | 資料表 | SCAN921260 X6 1:10 Deserializer with IEEE 1149.1 (JTAG) and at-speed BIST datasheet (Rev. F) | 2013/4/15 | |||
| 應用說明 | How to Validate BLVDS SER/DES Signal Integrity Using an Eye Mask (Rev. A) | 2013/4/26 |
設計與開發
如需其他條款或必要資源，請按一下下方的任何標題以檢視詳細頁面 (如有)。
| 封裝 | 針腳 | CAD 符號、佔位空間與 3D 模型 |
|---|---|---|
| NFBGA (NZH) | 196 | Ultra Librarian |