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SN54ABT125

現行

具有 TTL 相容 CMOS 輸入和 3 態輸出的軍用 4 通道、4.5-V 至 5.5-V 緩衝器

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產品規格表

SN54ABT125

現行
產品規格表 立即訂購

產品詳細資料

Technology family ABT Number of channels 4 IOL (max) (mA) 64 Supply current (max) (µA) 250 IOH (max) (mA) -32 Input type TTL-Compatible CMOS Output type 3-State Features Over-voltage tolerant inputs, Partial power down (Ioff), Power up 3-state, Ultra high speed (tpd <5ns) Rating Military Operating temperature range (°C) -55 to 125
Technology family ABT Number of channels 4 IOL (max) (mA) 64 Supply current (max) (µA) 250 IOH (max) (mA) -32 Input type TTL-Compatible CMOS Output type 3-State Features Over-voltage tolerant inputs, Partial power down (Ioff), Power up 3-state, Ultra high speed (tpd <5ns) Rating Military Operating temperature range (°C) -55 to 125
CFP (W) 14 58.023 mm² (— mm × — mm) CDIP (J) 14 130.4652 mm² (— mm × — mm) LCCC (FK) 20 79.0321 mm² (— mm × — mm)
  • Typical VOLP (Output Ground Bounce)
       <1 V at VCC = 5 V, TA = 25°C
  • High-Drive Outputs (–32-mA IOH, 64-mA IOL)
  • Ioff and Power-Up 3-State Support Hot Insertion
  • Latch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD-17
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)
  • Typical VOLP (Output Ground Bounce)
       <1 V at VCC = 5 V, TA = 25°C
  • High-Drive Outputs (–32-mA IOH, 64-mA IOL)
  • Ioff and Power-Up 3-State Support Hot Insertion
  • Latch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD-17
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)

The ’ABT125 quadruple bus buffer gates feature independent line drivers with 3-state outputs. Each output is disabled when the associated output-enable (OE)\ input is high.

These devices are fully specified for hot-insertion applications using Ioff and power-up 3-state. The Ioff circuitry disables the outputs, preventing damaging current backflow through the devices when they are powered down. The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down, which prevents driver conflict.

To ensure the high-impedance state during power up or power down, OE\ should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

The ’ABT125 quadruple bus buffer gates feature independent line drivers with 3-state outputs. Each output is disabled when the associated output-enable (OE)\ input is high.

These devices are fully specified for hot-insertion applications using Ioff and power-up 3-state. The Ioff circuitry disables the outputs, preventing damaging current backflow through the devices when they are powered down. The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down, which prevents driver conflict.

To ensure the high-impedance state during power up or power down, OE\ should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
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SN74HCT125 現行 具有 TTL 相容 CMOS 輸入和 3 態輸出的 4 通道、4.5-V 至 5.5-V 緩衝器 Voltage range 4.5V to 5.5V, average propagation delay 22ns, average drive strength 4mA

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重要文件 類型 標題 格式選項 下載最新的英文版本 日期
* 資料表 SN54ABT125, SN74ABT125 datasheet (Rev. I) 2002/10/30
* SMD SN54ABT125 SMD 5962-96768 2016/6/21

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封裝 針腳 CAD 符號、佔位空間與 3D 模型
CFP (W) 14 Ultra Librarian
CDIP (J) 14 Ultra Librarian
LCCC (FK) 20 Ultra Librarian
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