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HDMI、顯示介面和 MIPI IC

SN65DSI85-Q1

現行

連接雙鏈路 Flatlink™ LVDS 橋接器的汽車雙通道 MIPI DSI

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產品規格表

SN65DSI85-Q1

現行
產品規格表 立即訂購

產品詳細資料

Type Bridge Protocols LVDS, MIPI DSI Rating Automotive Speed (max) (Gbpp) 8 Operating temperature range (°C) -40 to 105
Type Bridge Protocols LVDS, MIPI DSI Rating Automotive Speed (max) (Gbpp) 8 Operating temperature range (°C) -40 to 105
HTQFP (PAP) 64 144 mm² (12 mm × 12 mm)
  • Qualified for Automotive Applications
  • AEC-Q100 Qualified With the Following Results:
    • Device Temperature Grade 2: –40°C to 105°C Ambient Operating Temperature
    • Device HBM ESD Classification Level 3A
    • Device CDM ESD Classification Level C6
  • Implements MIPI D-PHY Version 1.00.00 Physical Layer Front-End and Display Serial Interface (DSI) Version 1.02.00
  • Dual-Channel DSI Receiver Configurable for One, Two, Three, or Four D-PHY Data Lanes Per Channel Operating up to 1 Gbps Per Lane
  • Supports 18-bpp and 24-bpp DSI Video Packets with RGB666 and RGB888 Formats
  • Suitable for 60-fps WQXGA 2560 × 1600 Resolution at 18-bpp and 24-bpp Color, and 60 fps (120 fps Equivalent) WUXGA 1920 × 1200 Resolution With 3D Graphics at 24-bpp Color
  • MIPI Front-End Configurable for Single-Channel or Dual-Channel DSI Configurations
  • Output Configurable for Single-Link or Dual-Link LVDS
  • Supports Dual-Channel DSI ODD or EVEN and LEFT or RIGHT Operating Modes
  • Supports Two Single-Channel DSI to Two Single-Link LVDS Operating Mode
  • LVDS Output-Clock Range of 25 MHz to 154 MHz in Dual-Link or Single-Link Mode
  • LVDS Pixel Clock May be Sourced from Free-Running Continuous D-PHY Clock or External Reference Clock (REFCLK)
  • 1.8-V Main VCC Power Supply
  • Low Power Features Include SHUTDOWN Mode, Reduced LVDS Output Voltage Swing, Common Mode, and MIPI Ultra-Low Power State (ULPS) Support
  • LVDS Channel SWAP, LVDS PIN Order Reverse Feature for Ease of PCB Routing
  • Packaged in 64-pin 10 mm × 10 mm HTQFP (PAP) PowerPAD™ IC Package
  • Qualified for Automotive Applications
  • AEC-Q100 Qualified With the Following Results:
    • Device Temperature Grade 2: –40°C to 105°C Ambient Operating Temperature
    • Device HBM ESD Classification Level 3A
    • Device CDM ESD Classification Level C6
  • Implements MIPI D-PHY Version 1.00.00 Physical Layer Front-End and Display Serial Interface (DSI) Version 1.02.00
  • Dual-Channel DSI Receiver Configurable for One, Two, Three, or Four D-PHY Data Lanes Per Channel Operating up to 1 Gbps Per Lane
  • Supports 18-bpp and 24-bpp DSI Video Packets with RGB666 and RGB888 Formats
  • Suitable for 60-fps WQXGA 2560 × 1600 Resolution at 18-bpp and 24-bpp Color, and 60 fps (120 fps Equivalent) WUXGA 1920 × 1200 Resolution With 3D Graphics at 24-bpp Color
  • MIPI Front-End Configurable for Single-Channel or Dual-Channel DSI Configurations
  • Output Configurable for Single-Link or Dual-Link LVDS
  • Supports Dual-Channel DSI ODD or EVEN and LEFT or RIGHT Operating Modes
  • Supports Two Single-Channel DSI to Two Single-Link LVDS Operating Mode
  • LVDS Output-Clock Range of 25 MHz to 154 MHz in Dual-Link or Single-Link Mode
  • LVDS Pixel Clock May be Sourced from Free-Running Continuous D-PHY Clock or External Reference Clock (REFCLK)
  • 1.8-V Main VCC Power Supply
  • Low Power Features Include SHUTDOWN Mode, Reduced LVDS Output Voltage Swing, Common Mode, and MIPI Ultra-Low Power State (ULPS) Support
  • LVDS Channel SWAP, LVDS PIN Order Reverse Feature for Ease of PCB Routing
  • Packaged in 64-pin 10 mm × 10 mm HTQFP (PAP) PowerPAD™ IC Package

The SN65DSI85-Q1 DSI-to-LVDS bridge features a dual-channel MIPI D-PHY receiver front-end
configuration with four lanes per channel operating at 1 Gbps per lane and a maximum input bandwidth of 8 Gbps. The bridge decodes MIPI DSI 18-bpp RGB666 and 24-bpp RGB888 packets and converts the formatted video data-stream to an LVDS output operating at pixel clocks operating from 25 MHz to 154 MHz, offering a dual-link LVDS, single-link LVDS, or two Single-Link LVDS interfaces with four data lanes per link.

The SN65DSI85-Q1 device is well suited for WQXGA (2560 × 1600) at 60 frames per second (fps), as well as 3D Graphics at WUXGA and True HD (1920 × 1080) resolutions at an equivalent 120 fps with up to 24 bits-per-pixel (bpp). Partial line buffering is implemented to accommodate the data stream mismatch between the DSI and LVDS interfaces.

The SN65DSI85-Q1 device is implemented in a small outline 10 mm × 10 mm HTQFP package with a
0.5-mm pitch, and operates across a temperature range from –40°C to 105°C.

The SN65DSI85-Q1 DSI-to-LVDS bridge features a dual-channel MIPI D-PHY receiver front-end
configuration with four lanes per channel operating at 1 Gbps per lane and a maximum input bandwidth of 8 Gbps. The bridge decodes MIPI DSI 18-bpp RGB666 and 24-bpp RGB888 packets and converts the formatted video data-stream to an LVDS output operating at pixel clocks operating from 25 MHz to 154 MHz, offering a dual-link LVDS, single-link LVDS, or two Single-Link LVDS interfaces with four data lanes per link.

The SN65DSI85-Q1 device is well suited for WQXGA (2560 × 1600) at 60 frames per second (fps), as well as 3D Graphics at WUXGA and True HD (1920 × 1080) resolutions at an equivalent 120 fps with up to 24 bits-per-pixel (bpp). Partial line buffering is implemented to accommodate the data stream mismatch between the DSI and LVDS interfaces.

The SN65DSI85-Q1 device is implemented in a small outline 10 mm × 10 mm HTQFP package with a
0.5-mm pitch, and operates across a temperature range from –40°C to 105°C.

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SN65DSI84-Q1 現行 連接雙鏈路 LVDS 橋接器的汽車單通道 MIPI® DSI Supports 8 Gbps rather than 12 Gbps

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重要文件 類型 標題 格式選項 下載最新的英文版本 日期
* 資料表 SN65DSI85-Q1 Automotive Dual-Channel MIPI DSI to Dual-Link LVDS Bridge datasheet (Rev. B) PDF | HTML 2018/6/28
應用說明 Troubleshooting SN65DSI8x - Tips and Tricks 2018/8/27

設計與開發

如需其他條款或必要資源，請按一下下方的任何標題以檢視詳細頁面 (如有)。

開發板

SN65DSI85Q1-EVM — 雙通道 MIPI®；DSI 轉 Dual-Link FlatLink™；LVDS 橋接評估模組

SN65DSI85Q1EVM 是一款 PCB，專為協助客戶在系統硬體中實作 SN65DSI85Q1 所建立。  此 EVM 包含用於 DSI 輸入與 LVDS 輸出訊號的板上連接器。  這些連接器用於將符合 MIPI DPHY 標準的 DSI 來源和 LVDS 面板連接至 EVM。
使用指南: PDF
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參考設計

TIDA-01453 — 適用於車載資通訊系統車頭元件的 MIPI ® DSI 至 OLDI/LVDS 橋接器參考設計

此參考設計提供了兩種顯示介面選項：一種是帶有 MIPI® DSI 輸出的汽車處理器，另一種是帶有 OpenLDI (OLDI) / LVDS 輸入的汽車資訊娛樂視頻顯示面板。該參考設計提供了兩種變體。設定一將晶片系統 (SoC) DSI 視訊輸出訊號轉換為 OLDI/LVDS 視訊訊號，然後直接連接至整合式顯示器應用的面板上。設定二採用 FPD-Link III SerDes 技術，I²C 透過長纜線將 OLDI/LVDS 視訊訊號及 I²C 控制訊號傳送至面板，以供遠端顯示器應用使用。
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HTQFP (PAP) 64 Ultra Librarian
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