SN65ELT23
- Dual 5-V Differential PECL-to-TTL Buffer
- 24-mA TTL Ouputs
- Operating Range
- PECL VCC = 4.75 V to 5.25 V with GND = 0 V
- Support for Clock Frequencies of 250 MHz (TYP)
- 3.5-ns Typical Propagation Delay
- Output Default Low with Inputs Left Open or <1.3 V
- Internal Input 50-k
Pull-Down Resistor - Built-In Temperature Compensation
- Drop-In Compatible to the MC100ELT23
- APPLICATIONS
- Data and Clock Transmission Over Backplane
- Signaling Level Conversion for Clock or Data
The SN65ELT23 is a low power dual PECL-to-TTL translator device. The device includes circuitry to maintain a known logic low level when inputs are in an open condition. The SN65ELT23 is housed in an industry standard SOIC-8 package and is also available in an optional TSSOP-8 package.
技術文件
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| 重要文件 | 類型 | 標題 | 格式選項 | 下載最新的英文版本 | 日期 | |
|---|---|---|---|---|---|---|
| * | 資料表 | 5-V Dual Differential PECL Buffer-to-TTL Translator datasheet | 2009/6/30 | |||
| 應用說明 | AC Coupling Between Differential LVPECL, LVDS, HSTL and CML (Rev. C) | 2007/10/17 |
設計與開發
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| 封裝 | 針腳 | CAD 符號、佔位空間與 3D 模型 |
|---|---|---|
| VSSOP (DGK) | 8 | Ultra Librarian |
| SOIC (D) | 8 | Ultra Librarian |