SN65LV1224B

現行

1:10 LVDS 串聯器/解串器接收器 100 - 660Mbps

產品詳細資料

Function Deserializer Protocols Channel-Link I Signaling rate (Mbps) 660 Input signal LVCMOS, LVTTL Output signal LVDS Rating Catalog Operating temperature range (°C) -40 to 85
Function Deserializer Protocols Channel-Link I Signaling rate (Mbps) 660 Input signal LVCMOS, LVTTL Output signal LVDS Rating Catalog Operating temperature range (°C) -40 to 85
VQFN (RHB) 32 25 mm² (5 mm × 5 mm) SSOP (DB) 28 79.56 mm² (10.2 mm × 7.8 mm)
  • 100-Mbps to 660-Mbps Serial LVDS Data Payload Bandwidth at 10-MHz
    to 66-MHz System Clock
  • Pin-Compatible Superset of DS92LV1023/DS92LV1224
  • Chipset (Serializer/Deserializer) Power Consumption <450 mW (Typ) at 66 MHz
  • Synchronization Mode for Faster Lock
  • Lock Indicator
  • No External Components Required for PLL
  • 28-Pin SSOP and Space Saving 5 × 5 mm QFN Packages Available
  • Industrial Temperature Qualified,
    TA = −40°C to 85°C
  • Programmable Edge Trigger on Clock
  • Flow-Through Pinout for Easy PCB Layout
  • APPLICATIONS
    • Wireless Base Station
    • Backplane Interconnect
    • DSLAM

  • 100-Mbps to 660-Mbps Serial LVDS Data Payload Bandwidth at 10-MHz
    to 66-MHz System Clock
  • Pin-Compatible Superset of DS92LV1023/DS92LV1224
  • Chipset (Serializer/Deserializer) Power Consumption <450 mW (Typ) at 66 MHz
  • Synchronization Mode for Faster Lock
  • Lock Indicator
  • No External Components Required for PLL
  • 28-Pin SSOP and Space Saving 5 × 5 mm QFN Packages Available
  • Industrial Temperature Qualified,
    TA = −40°C to 85°C
  • Programmable Edge Trigger on Clock
  • Flow-Through Pinout for Easy PCB Layout
  • APPLICATIONS
    • Wireless Base Station
    • Backplane Interconnect
    • DSLAM

The SN65LV1023A serializer and SN65LV1224B deserializer comprise a 10-bit serdes chipset designed to transmit and receive serial data over LVDS differential backplanes at equivalent parallel word rates from 10 MHz to 66 MHz. Including overhead, this translates into a serial data rate between 120-Mbps and 792-Mbps payload encoded throughput.

Upon power up, the chipset link can be initialized via a synchronization mode with internally generated SYNC patterns or the deserializer can be allowed to synchronize to random data. By using the synchronization mode, the deserializer establishes lock within specified, shorter time parameters.

The device can be entered into a power-down state when no data transfer is required. Alternatively, a mode is available to place the output pins in the high-impedance state without losing PLL lock.

The SN65LV1023A and SN65LV1224B are characterized for operation over ambient air temperature of –40°C to 85°C.

The SN65LV1023A serializer and SN65LV1224B deserializer comprise a 10-bit serdes chipset designed to transmit and receive serial data over LVDS differential backplanes at equivalent parallel word rates from 10 MHz to 66 MHz. Including overhead, this translates into a serial data rate between 120-Mbps and 792-Mbps payload encoded throughput.

Upon power up, the chipset link can be initialized via a synchronization mode with internally generated SYNC patterns or the deserializer can be allowed to synchronize to random data. By using the synchronization mode, the deserializer establishes lock within specified, shorter time parameters.

The device can be entered into a power-down state when no data transfer is required. Alternatively, a mode is available to place the output pins in the high-impedance state without losing PLL lock.

The SN65LV1023A and SN65LV1224B are characterized for operation over ambient air temperature of –40°C to 85°C.

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重要文件 類型 標題 格式選項 下載最新的英文版本 日期
* 資料表 10-MHz to 66-MHz, 10:1-LVDS Serializer/Deserializer datasheet (Rev. E) 2009/12/7
應用說明 Applications of Low-Voltage Differential Signaling (LVDS) in LED Walls 2020/10/29
Application brief Migrating from DS92LV1021A/1212A 10-bit SerDes to SN65LV1023A/1224B 2018/11/15
使用指南 10:1 Serializer/Deserializer Evaluation Board 2013/11/20

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VQFN (RHB) 32 Ultra Librarian
SSOP (DB) 28 Ultra Librarian

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