SN65LVDS93A
- Industrial Temperature Range –40°C to 85°C
- LVDS Display Serdes Interfaces Directly to LCD
Display Panels With Integrated LVDS - Package Options: 4.5-mm × 7-mm BGA, and 8.1-
mm × 14-mm TSSOP - 1.8 V up to 3.3-V Tolerant Data Inputs to Connect
Directly to Low-Power, Low-Voltage Application
and Graphic Processors - Transfer Rate up to 135 Mpps (Mega Pixels Per
Second); Pixel Clock Frequency Range 10 MHz to
135 MHz - Suited for Display Resolutions Ranging From
HVGA up to HD With Low EMI - Operates From a Single 3.3-V Supply and 170
mW (Typical) at 75 MHz - 28 Data Channels Plus Clock In Low-Voltage TTL
to 4 Data Channels Plus Clock Out Low-Voltage
Differential - Consumes Less Than 1 mW When Disabled
- Selectable Rising or Falling Clock Edge Triggered
Inputs - ESD: 5-kV HBM
- Supports Spread Spectrum Clocking (SSC)
- Compatible With all OMAP™2x, OMAP3x, and
DaVinci™ Application Processors
The SN65LVDS93A LVDS SerDes (serializer/deserializer) transmitter contains four 7-bit parallel load serial-out shift registers, a 7 × clock synthesizer, and five low-voltage differential signaling (LVDS) drivers in a single integrated circuit. These functions allow synchronous transmission of 28 bits of single-ended LVTTL data over five balanced-pair conductors for receipt by a compatible receiver, such as the SN65LVDS94 (SLLS928).
When transmitting, data bits D0 through D27 are each loaded into registers upon the edge of the input clock signal (CLKIN). The rising or falling edge of the clock can be selected through the clock select (CLKSEL) pin. The frequency of CLKIN is multiplied seven times and then used to serially unload the data registers in 7-bit slices. The four serial streams and a phase-locked clock (CLKOUT) are then output to LVDS output drivers. The frequency of CLKOUT is the same as the input clock, CLKIN.
The SN65LVDS93A device requires no external components and little or no control. The data bus appears the same at the input to the transmitter and output of the receiver with the data transmission transparent to the users. The only user intervention is selecting a clock rising edge by inputting a high level to CLKSEL or a falling edge with a low-level input and the possible use of the shutdown/clear (SHTDN) signal. SHTDN is an active-low input to inhibit the clock and shut off the LVDS output drivers for lower power consumption. A low level on this signal clears all internal registers at a low level.
The SN65LVDS93A is characterized for operation over ambient air temperatures of –40°C to 85°C.
技術文件
| 重要文件 | 類型 | 標題 | 格式選項 | 下載最新的英文版本 | 日期 | |
|---|---|---|---|---|---|---|
| * | 資料表 | SN65LVDS93A FlatLink™ Transmitter datasheet (Rev. B) | PDF | HTML | 2015/3/30 | ||
| 應用說明 | High-Speed Layout Guidelines for Reducing EMI for LVDS SerDes Designs | 2018/11/9 | ||||
| 技術文章 | Finding the right pixel clock frequency and throughput for an LVDS display resolut | PDF | HTML | 2018/9/26 | |||
| 應用說明 | AN-1108 Channel-Link PCB and Interconnect Design-In Guidelines (Rev. A) | 2018/8/3 |
設計與開發
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LVDS83BTSSOPEVM — LVDS83BT 10-135 MHz 28 位元 LVDS 發送器/串聯器評估模組
| 封裝 | 針腳 | CAD 符號、佔位空間與 3D 模型 |
|---|---|---|
| TSSOP (DGG) | 56 | Ultra Librarian |
訂購與品質
建議產品可能具有與此 TI 產品相關的參數、評估模組或參考設計。