SN65LVDT41
- Integrated 110-Ω nominal receiver line termination resistor
- Single 3.3-V power supply (3-V to 3.6-V range)
- Supports signaling rates of at least 250 Mbps
- Flow-through pinout simplifies PCB layout
- LVTTL-compatible logic I/Os
- ESD protection on bus pins exceeds 16 kV
- Meets or exceeds the requirements of ANSI/TIA/EIA-644A standard for LVDS
- 20-pin PW thin shrink small-outline package with 26-mil terminal pitch
The SN65LVDTxx devices are multi-channel LVDS transceivers that operate using LVDS line drivers and receivers. The SN65LVDTxx devices support signaling rates of at least 250 Mbps, and the devices operate from a single supply (typically at 3.3 V) in a 20-pin TSSOP package designed for easy PCB layout.
The SN65LVDT14 and SN65LVDT41 provide general-purpose, asymmetric, bidirectional communication with the added benefit of high noise immunity, low electromagnetic interference (EMI), and increased cable length through the use of LVDS lines. The SN65LVDT14 and SN65LVDT41 are primarily used for SPI over LVDS applications.
The SN65LVDT14 combines one LVDS line driver with four terminated LVDS line receivers in one package. The SN65LVDT14 can be used to extend asymmetric, bidirectional interfaces such as SPI over long distances, and should be located at the SPI slave.
The SN65LVDT41 combines four LVDS line drivers with a single terminated LVDS line receiver in one package. The SN65LVDT41 can be used to extend asymmetric, bidirectional interfaces such as SPI over long distances, and should be located at the SPI master.
技術文件
| 類型 | 標題 | 日期 | ||
|---|---|---|---|---|
| * | Data sheet | SN65LVDTxx multi-channel LVDS transceivers SN65LVDT14—One LVDS driver plus four LVDS receivers SN65LVDT41—Four LVDS drivers plus one LVDS receiver datasheet (Rev. C) | PDF | HTML | 2019年 2月 7日 |
| Application brief | LVDS to Improve EMC in Motor Drives | 2018年 9月 27日 | ||
| Application brief | How Far, How Fast Can You Operate LVDS Drivers and Receivers? | 2018年 8月 3日 | ||
| Application brief | How to Terminate LVDS Connections with DC and AC Coupling | 2018年 5月 16日 |
設計與開發
如需其他條款或必要資源，請按一下下方的任何標題以檢視詳細頁面 (如有)。
PSPICE-FOR-TI — PSpice® for TI 設計與模擬工具
PSpice for TI 設計和模擬環境可讓您使用其內建函式庫來模擬複雜的混合訊號設計。在進行佈局和製造之前，建立完整的終端設備設計和解決方案原型，進而縮短上市時間並降低開發成本。
在 PSpice for TI 設計與模擬工具中，您可以搜尋 TI (...)
TINA-TI — 基於 SPICE 的類比模擬程式
| 封裝 | 針腳 | CAD 符號、佔位空間與 3D 模型 |
|---|---|---|
| TSSOP (PW) | 20 | Ultra Librarian |
訂購與品質
- RoHS
- REACH
- 產品標記
- 鉛塗層/球物料
- MSL 等級/回焊峰值
- MTBF/FIT 估算值
- 材料內容
- 認證摘要
- 進行中持續性的可靠性監測
- 晶圓廠位置
- 組裝地點
建議產品可能具有與此 TI 產品相關的參數、評估模組或參考設計。