SN65LVP17

現行

具有啟用功能的 2.5-V/3.3-V 振盪器增益級/緩衝器

產品詳細資料

Function Buffer, Translator Protocols LVPECL Number of transmitters 1 Number of receivers 1 Supply voltage (V) 2.5, 3.3 Signaling rate (MBits) 4000 Input signal Differential Output signal LVPECL Rating Catalog Operating temperature range (°C) -40 to 85
Function Buffer, Translator Protocols LVPECL Number of transmitters 1 Number of receivers 1 Supply voltage (V) 2.5, 3.3 Signaling rate (MBits) 4000 Input signal Differential Output signal LVPECL Rating Catalog Operating temperature range (°C) -40 to 85
WSON (DRF) 8 4 mm² 2 x 2
  • Low-Voltage PECL Input and Low-Voltage PECL or LVDS Outputs
  • Clock Rates to 2 GHz
    • 140-ps Output Transition Times
    • 0.11 ps Typical Intrinsic Phase Jitter
    • Less than 630 ps Propagation Delay Times
  • 2.5-V or 3.3-V Supply Operation
  • 2-mm × 2-mm Small-Outline No-Lead Package
  • APPLICATIONS
    • PECL-to-LVDS Translation
    • Clock Signal Amplification

  • Low-Voltage PECL Input and Low-Voltage PECL or LVDS Outputs
  • Clock Rates to 2 GHz
    • 140-ps Output Transition Times
    • 0.11 ps Typical Intrinsic Phase Jitter
    • Less than 630 ps Propagation Delay Times
  • 2.5-V or 3.3-V Supply Operation
  • 2-mm × 2-mm Small-Outline No-Lead Package
  • APPLICATIONS
    • PECL-to-LVDS Translation
    • Clock Signal Amplification

These four devices are high-frequency oscillator gain stages supporting both LVPECL or LVDS on the high gain outputs in 3.3-V or 2.5-V systems. Additionally, provides the option of both single-ended input (PECL levels on the SN65LVx16) and fully differential inputs on the SN65LVx17.

The SN65LVx16 provides the user a Gain Control (GC) for controlling the Q output from 300 mV to 860 mV either by leaving it open (NC), grounded, or tied to VCC. (When left open, the Q output defaults to 575 mV.) The Q on the SN65LVx17 defaults to 575 mV as well.

Both devices provide a voltage reference (VBB) of typically 1.35 V below VCC for use in receiving single-ended PECL input signals. When not used, VBB should be unconnected or open.

All devices are characterized for operation from -40°C to 85°C.

These four devices are high-frequency oscillator gain stages supporting both LVPECL or LVDS on the high gain outputs in 3.3-V or 2.5-V systems. Additionally, provides the option of both single-ended input (PECL levels on the SN65LVx16) and fully differential inputs on the SN65LVx17.

The SN65LVx16 provides the user a Gain Control (GC) for controlling the Q output from 300 mV to 860 mV either by leaving it open (NC), grounded, or tied to VCC. (When left open, the Q output defaults to 575 mV.) The Q on the SN65LVx17 defaults to 575 mV as well.

Both devices provide a voltage reference (VBB) of typically 1.35 V below VCC for use in receiving single-ended PECL input signals. When not used, VBB should be unconnected or open.

All devices are characterized for operation from -40°C to 85°C.

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技術文件

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類型 標題 日期
* Data sheet 2.5-V/3.3-V Oscillator Gain Stage/Buffers datasheet (Rev. B) 2005年 11月 18日
EVM User's guide Translator/Oscillator Buffer EVM (Rev. A) 2004年 9月 17日

設計與開發

如需其他條款或必要資源,請按一下下方的任何標題以檢視詳細頁面 (如有)。

模擬型號

SN65LVP17 with Gain Control GC tied to GND IBIS Model

SLLC235.ZIP (11 KB) - IBIS Model
模擬型號

SN65LVP17 with Gain Control GC tied to NC IBIS Model

SLLC236.ZIP (10 KB) - IBIS Model
模擬型號

SN65LVP17 with Gain Control GC tied to VCC IBIS Model

SLLC237.ZIP (11 KB) - IBIS Model
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