TB5R2

現行

四路 PECL 線路接收器

產品詳細資料

Function Receiver Protocols PECL Number of transmitters 0 Number of receivers 4 Supply voltage (V) 5 Signaling rate (Mbps) 100 Input signal PECL Output signal TTL Rating Catalog Operating temperature range (°C) -40 to 85
Function Receiver Protocols PECL Number of transmitters 0 Number of receivers 4 Supply voltage (V) 5 Signaling rate (Mbps) 100 Input signal PECL Output signal TTL Rating Catalog Operating temperature range (°C) -40 to 85
SOIC (D) 16 59.4 mm² 9.9 x 6 SOIC (DW) 16 106.09 mm² 10.3 x 10.3
  • Functional Replacements for the Agere BRF1A, BRF2A, BRS2A, and BRS2B
  • Pin Equivalent to General Trade 26LS32
  • High Input Impedance Approximately 8 k
  • 4-ns Maximum Propagation Delay
  • TB5R1 Provides 50-mV Hysteresis
  • TB5R2 With -125-mV Threshold Offset for Preferred State Output
  • -1.1-V to 7.1-V Common Mode Range
  • Single 5-V ±10% Supply
  • Slew Rate Limited (1 ns min 80% to 20%)
  • TB5R2 Output Defaults to Logic 1 When Inputs Left Open or Shorted to VCC or GND
  • ESD Protection HBM > 3 kV, CDM > 2 kV
  • Operating Temperature Range: -40°C to 85°C
  • Available in Gull-Wing SOIC (JEDEC MS-013, DW) and SOIC (D) Package
  • APPLICATIONS
    • Digital Data or Clock Transmission Over Balanced Lines

  • Functional Replacements for the Agere BRF1A, BRF2A, BRS2A, and BRS2B
  • Pin Equivalent to General Trade 26LS32
  • High Input Impedance Approximately 8 k
  • 4-ns Maximum Propagation Delay
  • TB5R1 Provides 50-mV Hysteresis
  • TB5R2 With -125-mV Threshold Offset for Preferred State Output
  • -1.1-V to 7.1-V Common Mode Range
  • Single 5-V ±10% Supply
  • Slew Rate Limited (1 ns min 80% to 20%)
  • TB5R2 Output Defaults to Logic 1 When Inputs Left Open or Shorted to VCC or GND
  • ESD Protection HBM > 3 kV, CDM > 2 kV
  • Operating Temperature Range: -40°C to 85°C
  • Available in Gull-Wing SOIC (JEDEC MS-013, DW) and SOIC (D) Package
  • APPLICATIONS
    • Digital Data or Clock Transmission Over Balanced Lines

These quad differential receivers accept digital data over balanced transmission lines. They translate differential input logic levels to TTL output logic levels.

The TB5R1 is a pin- and function-compatible replacement for the Agere systems BRF1A and BRF2A; it includes 3-kV HBM and 2-kV CDM ESD protection.

The TB5R2 is a pin- and function-compatible replacement for the Agere systems BRS2A and BRS2B and incorporates a 125-mV receiver input offset, preferred state output, 3-kV HBM and 2-kV CDM ESD protection. The TB5R2 preferred state feature places the high state when the inputs are open, shorted to ground, or shorted to the power supply.

The power-down loading characteristics of the receiver input circuit are approximately 8 k relative to the power supplies; hence they do not load the transmission line when the circuit is powered down.

The packaging for these differential line receivers include a 16-pin gull wing SOIC (DW) and SOIC (D).

The enable inputs of this device include internal pullup resistors of approximately 40 k that are connected to VCC to ensure a logical high level input if the inputs are open circuited.

These quad differential receivers accept digital data over balanced transmission lines. They translate differential input logic levels to TTL output logic levels.

The TB5R1 is a pin- and function-compatible replacement for the Agere systems BRF1A and BRF2A; it includes 3-kV HBM and 2-kV CDM ESD protection.

The TB5R2 is a pin- and function-compatible replacement for the Agere systems BRS2A and BRS2B and incorporates a 125-mV receiver input offset, preferred state output, 3-kV HBM and 2-kV CDM ESD protection. The TB5R2 preferred state feature places the high state when the inputs are open, shorted to ground, or shorted to the power supply.

The power-down loading characteristics of the receiver input circuit are approximately 8 k relative to the power supplies; hence they do not load the transmission line when the circuit is powered down.

The packaging for these differential line receivers include a 16-pin gull wing SOIC (DW) and SOIC (D).

The enable inputs of this device include internal pullup resistors of approximately 40 k that are connected to VCC to ensure a logical high level input if the inputs are open circuited.

下載 觀看有字幕稿的影片 影片

技術文件

star =TI 所選的此產品重要文件
找不到結果。請清除您的搜尋條件,然後再試一次。
檢視所有 1
類型 標題 日期
* Data sheet TB5R1,TB5R2, Quad Differential PECL Receivers datasheet (Rev. C) 2008年 1月 18日

設計與開發

如需其他條款或必要資源,請按一下下方的任何標題以檢視詳細頁面 (如有)。

模擬型號

TB5R2D IBIS Model

SLLC202.ZIP (9 KB) - IBIS Model
模擬型號

TB5R2DW IBIS Model

SLLC203.ZIP (9 KB) - IBIS Model
模擬工具

PSPICE-FOR-TI — PSpice® for TI 設計與模擬工具

PSpice® for TI 是有助於評估類比電路功能的設計和模擬環境。這款全功能設計和模擬套件使用 Cadence® 的類比分析引擎。PSpice for TI 包括業界最大的模型庫之一,涵蓋我們的類比和電源產品組合,以及特定類比行為模型,且使用無需支付費用。

PSpice for TI 設計和模擬環境可讓您使用其內建函式庫來模擬複雜的混合訊號設計。在進行佈局和製造之前,建立完整的終端設備設計和解決方案原型,進而縮短上市時間並降低開發成本。 

在 PSpice for TI 設計與模擬工具中,您可以搜尋 TI (...)
模擬工具

TINA-TI — 基於 SPICE 的類比模擬程式

TINA-TI provides all the conventional DC, transient and frequency domain analysis of SPICE and much more. TINA has extensive post-processing capability that allows you to format results the way you want them. Virtual instruments allow you to select input waveforms and probe circuit nodes voltages (...)
使用指南: PDF
封裝 針腳 CAD 符號、佔位空間與 3D 模型
SOIC (D) 16 Ultra Librarian
SOIC (DW) 16 Ultra Librarian

訂購與品質

內含資訊:
  • RoHS
  • REACH
  • 產品標記
  • 鉛塗層/球物料
  • MSL 等級/回焊峰值
  • MTBF/FIT 估算值
  • 材料內容
  • 認證摘要
  • 進行中持續性的可靠性監測
內含資訊:
  • 晶圓廠位置
  • 組裝地點

支援與培訓

內含 TI 工程師技術支援的 TI E2E™ 論壇

內容係由 TI 和社群貢獻者依「現狀」提供,且不構成 TI 規範。檢視使用條款

若有關於品質、封裝或訂購 TI 產品的問題,請參閱 TI 支援。​​​​​​​​​​​​​​

影片